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Samsung DeviceTree ARM update for v4.12: 

1. Enhancements to PCIe nodes on Exynos5440.
 2. Fix thermal values on some of Exynos5420 boards like Odroid XU3.
 3. Add proper clock frequency properties to DSI nodes.
 4. Fix watchdog reset on Exynos4412.
 5. Fix watchdog infinite interrupt in soft mode on Exynos4210,
    Exynos5440, S3C64xx and S5Pv210.
 6. Enable watchdog on Exynos4 and S3C SoCs.
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Merge tag 'samsung-dt-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt

Samsung DeviceTree ARM update for v4.12:
1. Enhancements to PCIe nodes on Exynos5440.
2. Fix thermal values on some of Exynos5420 boards like Odroid XU3.
3. Add proper clock frequency properties to DSI nodes.
4. Fix watchdog reset on Exynos4412.
5. Fix watchdog infinite interrupt in soft mode on Exynos4210,
   Exynos5440, S3C64xx and S5Pv210.
6. Enable watchdog on Exynos4 and S3C SoCs.

* tag 'samsung-dt-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  ARM: dts: exynos: add HDMI controller phandle to exynos4.dtsi
  ARM: dts: s5pv210: Fix infinite interrupt in soft mode
  ARM: dts: s3c64xx: Fix infinite interrupt in soft mode
  ARM: dts: exynos: Fix infinite interrupt in soft mode on Exynos4210 and Exynos5440
  ARM: dts: exynos: Enable watchdog on all Exynos4 boards
  ARM: dts: s3c64xx: Enable watchdog on all S3C64xx boards
  ARM: dts: exynos: Fix watchdog reset on Exynos4412
  ARM: dts: exynos: Add the burst and esc clock frequency properties to DSI node
  ARM: dts: exynos: Do not ignore real-world fuse values for thermal zone 0 on Exynos5420
  ARM: dts: exynos: Add phy-pcie node for pcie to Exynos5440

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2017-04-19 06:44:37 -07:00
parent 107193765b a1146328ec
commit 6daf2aab1c
15 changed files with 77 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/exynos3250-rinato.dts
View File

@ -215,6 +215,8 @@
&dsi_0 {
vddcore-supply = <&ldo6_reg>;
vddio-supply = <&ldo6_reg>;
samsung,burst-clock-frequency = <250000000>;
samsung,esc-clock-frequency = <20000000>;
samsung,pll-clock-frequency = <24000000>;
status = "okay";

10
arch/arm/boot/dts/exynos4.dtsi
View File

@ -283,15 +283,6 @@
};
};
watchdog: watchdog@10060000 {
compatible = "samsung,s3c2410-wdt";
reg = <0x10060000 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_WDT>;
clock-names = "watchdog";
status = "disabled";
};
rtc: rtc@10070000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x10070000 0x100>;
@ -771,6 +762,7 @@
clocks = <&clock CLK_HDMI_CEC>;
clock-names = "hdmicec";
samsung,syscon-phandle = <&pmu_system_controller>;
hdmi-phandle = <&hdmi>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
status = "disabled";

4
arch/arm/boot/dts/exynos4210-origen.dts
View File

@ -328,7 +328,3 @@
&tmu {
status = "okay";
};
&watchdog {
status = "okay";
};

2
arch/arm/boot/dts/exynos4210-trats.dts
View File

@ -197,6 +197,8 @@
&dsi_0 {
vddcore-supply = <&vusb_reg>;
vddio-supply = <&vmipi_reg>;
samsung,burst-clock-frequency = <500000000>;
samsung,esc-clock-frequency = <20000000>;
samsung,pll-clock-frequency = <24000000>;
status = "okay";

8
arch/arm/boot/dts/exynos4210.dtsi
View File

@ -119,6 +119,14 @@
};
};
watchdog: watchdog@10060000 {
compatible = "samsung,s3c6410-wdt";
reg = <0x10060000 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_WDT>;
clock-names = "watchdog";
};
clock: clock-controller@10030000 {
compatible = "samsung,exynos4210-clock";
reg = <0x10030000 0x20000>;

4
arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
View File

@ -495,7 +495,3 @@
vtmu-supply = <&ldo16_reg>;
status = "okay";
};
&watchdog {
status = "okay";
};

4
arch/arm/boot/dts/exynos4412-odroid-common.dtsi
View File

@ -555,7 +555,3 @@
vtmu-supply = <&ldo10_reg>;
status = "okay";
};
&watchdog {
status = "okay";
};

4
arch/arm/boot/dts/exynos4412-origen.dts
View File

@ -541,7 +541,3 @@
&serial_3 {
status = "okay";
};
&watchdog {
status = "okay";
};

2
arch/arm/boot/dts/exynos4412-trats2.dts
View File

@ -385,6 +385,8 @@
&dsi_0 {
vddcore-supply = <&ldo8_reg>;
vddio-supply = <&ldo10_reg>;
samsung,burst-clock-frequency = <500000000>;
samsung,esc-clock-frequency = <20000000>;
samsung,pll-clock-frequency = <24000000>;
status = "okay";

9
arch/arm/boot/dts/exynos4412.dtsi
View File

@ -215,6 +215,15 @@
};
};
watchdog: watchdog@10060000 {
compatible = "samsung,exynos5250-wdt";
reg = <0x10060000 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_WDT>;
clock-names = "watchdog";
samsung,syscon-phandle = <&pmu_system_controller>;
};
adc: adc@126C0000 {
compatible = "samsung,exynos-adc-v1";
reg = <0x126C0000 0x100>;

25
arch/arm/boot/dts/exynos5420-tmu-sensor-conf.dtsi Normal file
View File

@ -0,0 +1,25 @@
/*
* Device tree sources for Exynos5420 TMU sensor configuration
*
* Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
* Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <dt-bindings/thermal/thermal_exynos.h>
#thermal-sensor-cells = <0>;
samsung,tmu_gain = <8>;
samsung,tmu_reference_voltage = <16>;
samsung,tmu_noise_cancel_mode = <4>;
samsung,tmu_efuse_value = <55>;
samsung,tmu_min_efuse_value = <0>;
samsung,tmu_max_efuse_value = <100>;
samsung,tmu_first_point_trim = <25>;
samsung,tmu_second_point_trim = <85>;
samsung,tmu_default_temp_offset = <50>;
samsung,tmu_cal_type = <TYPE_ONE_POINT_TRIMMING>;

10
arch/arm/boot/dts/exynos5420.dtsi
View File

@ -699,7 +699,7 @@
interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
#include "exynos5420-tmu-sensor-conf.dtsi"
};
tmu_cpu1: tmu@10064000 {
@ -708,7 +708,7 @@
interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>;
clock-names = "tmu_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
#include "exynos5420-tmu-sensor-conf.dtsi"
};
tmu_cpu2: tmu@10068000 {
@ -717,7 +717,7 @@
interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
#include "exynos5420-tmu-sensor-conf.dtsi"
};
tmu_cpu3: tmu@1006c000 {
@ -726,7 +726,7 @@
interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
#include "exynos5420-tmu-sensor-conf.dtsi"
};
tmu_gpu: tmu@100a0000 {
@ -735,7 +735,7 @@
interrupts = <0 215 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
#include "exynos4412-tmu-sensor-conf.dtsi"
#include "exynos5420-tmu-sensor-conf.dtsi"
};
sysmmu_g2dr: sysmmu@0x10A60000 {

32
arch/arm/boot/dts/exynos5440.dtsi
View File

@ -189,7 +189,7 @@
};
watchdog@110000 {
compatible = "samsung,s3c2410-wdt";
compatible = "samsung,s3c6410-wdt";
reg = <0x110000 0x1000>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_B_125>;
@ -290,11 +290,22 @@
clock-names = "usbhost";
};
pcie_phy0: pcie-phy@270000 {
#phy-cells = <0>;
compatible = "samsung,exynos5440-pcie-phy";
reg = <0x270000 0x1000>, <0x271000 0x40>;
};
pcie_phy1: pcie-phy@272000 {
#phy-cells = <0>;
compatible = "samsung,exynos5440-pcie-phy";
reg = <0x272000 0x1000>, <0x271040 0x40>;
};
pcie_0: pcie@290000 {
compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
reg = <0x290000 0x1000
0x270000 0x1000
0x271000 0x40>;
reg = <0x290000 0x1000>, <0x40000000 0x1000>;
reg-names = "elbi", "config";
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
@ -303,8 +314,8 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */
0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
phys = <&pcie_phy0>;
ranges = <0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
@ -315,9 +326,8 @@
pcie_1: pcie@2a0000 {
compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
reg = <0x2a0000 0x1000
0x272000 0x1000
0x271040 0x40>;
reg = <0x2a0000 0x1000>, <0x60000000 0x1000>;
reg-names = "elbi", "config";
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
@ -326,8 +336,8 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */
0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
phys = <&pcie_phy1>;
ranges = <0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;

3
arch/arm/boot/dts/s3c64xx.dtsi
View File

@ -94,13 +94,12 @@
};
watchdog: watchdog@7e004000 {
compatible = "samsung,s3c2410-wdt";
compatible = "samsung,s3c6410-wdt";
reg = <0x7e004000 0x1000>;
interrupt-parent = <&vic0>;
interrupts = <26>;
clock-names = "watchdog";
clocks = <&clocks PCLK_WDT>;
status = "disabled";
};
i2c0: i2c@7f004000 {

2
arch/arm/boot/dts/s5pv210.dtsi
View File

@ -310,7 +310,7 @@
};
watchdog: watchdog@e2700000 {
compatible = "samsung,s3c2410-wdt";
compatible = "samsung,s3c6410-wdt";
reg = <0xe2700000 0x1000>;
interrupt-parent = <&vic0>;
interrupts = <26>;