Devicetree changes for omap variants
This series of changes configures dra7 pcie x2 lane mode, configures am43xx-epos-evm regulators and keypad wakeup source, and uses standard reset-gpios instead of gpio-reset for n810. We also need to split dra7 dtsi files for properly supporting dra76x and am576 as some of the devices are different such as usb and pruss. -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAly0pfQRHHRvbnlAYXRv bWlkZS5jb20ACgkQG9Q+yVyrpXNM3BAAvrQsjq1NTq6k7L5yZuInYtP+L7isRTz3 M7AWpMOjXex+a3GoZ8a8qrRVc6IqohAid75y8Y1qDvFVi9QEMrCsYlRwlYl048UM o5Ry4CePIY9XvUurRIemisT5/RQ4jzz9BBPogIJeQHl9r4qKbZEzTllmHnE7D78i Eh52IHQKScyO5MmUxZErH2f2StPHINjvO5WeuUUGcDcg7pcRlnbgLDtx26deewbl qMCh/3u71vd0g1JyEScOSq/QkeASpDx0sJifCLeWOmRZyarQGg5SduxVnQ6OJo8U xqiQ5dNYEn4BASOZ6BFGmSyqjvQWgmA0RnxkGB9nYPk9s9Lafq+gWgFNrI99Eavm BERMXlsrOJ/y5STjx+wmZ/IEeUceNqHK44xr8hcYweiu1Duv8+lfRRLLOdj2besh SPYsomoqY1yQKvr3k7YcuCddsFQZ9RtcaLVjlJmNlDE078jI1f/v9ZLXY8K8ZF3G gm07S/HtuX7xWM/fRveXrP2YQ+OREoyo5cTeDAyZmk/bY3sqVwgRuicgXAqu0Zdg AJQCnNda4UAIohtC98RHS1MB5BuwTyv431iAsxaAvK2cAR8NnV3qr5AmBbgP1iMP /oLeXA6OpfT+JHk/tGQ0TG9LrqNqW9DyZZOqfXCGYTiRJd06qUxvPIZOsUQFnJho jIsDaa4YQjc= =uc0c -----END PGP SIGNATURE----- Merge tag 'omap-for-v5.2/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt Devicetree changes for omap variants This series of changes configures dra7 pcie x2 lane mode, configures am43xx-epos-evm regulators and keypad wakeup source, and uses standard reset-gpios instead of gpio-reset for n810. We also need to split dra7 dtsi files for properly supporting dra76x and am576 as some of the devices are different such as usb and pruss. * tag 'omap-for-v5.2/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: dra7: Separate AM57 dtsi files dt-binding: arm: omap: Add information for AM5748 ARM: dts: omap2420-n810: Use new CODEC reset pin name ARM: dts: am43xx-epos-evm: Add matrix keypad as wakeup source ARM: dts: am43xx-epos-evm: Keep DCDC3 regulator on in suspend to memory ARM: dts: am43xx-epos-evm: Keep DCDC5 and DCDC6 always on ARM: dts: dra7: Add properties to enable PCIe x2 lane mode Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
6d918e0933
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@ -92,6 +92,9 @@ SoCs:
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- DRA718
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compatible = "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7"
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- AM5748
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compatible = "ti,am5748", "ti,dra762", "ti,dra7"
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- AM5728
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compatible = "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
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@ -184,6 +187,9 @@ Boards:
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- AM57XX SBC-AM57x
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compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
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- AM5748 IDK
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compatible = "ti,am5748-idk", "ti,am5748", "ti,dra762", "ti,dra7";
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- AM5728 IDK
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compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
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@ -80,6 +80,7 @@
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&matrix_keypad_default>;
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pinctrl-1 = <&matrix_keypad_sleep>;
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wakeup-source;
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row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */
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&gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */
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@ -620,6 +621,12 @@
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regulator-name = "vdcdc3";
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regulator-boot-on;
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regulator-always-on;
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regulator-state-mem {
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regulator-on-in-suspend;
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};
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regulator-state-disk {
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regulator-off-in-suspend;
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};
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};
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dcdc4: regulator-dcdc4 {
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@ -634,12 +641,16 @@
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regulator-name = "v1_0bat";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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dcdc6: regulator-dcdc6 {
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regulator-name = "v1_8bat";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo1: regulator-ldo1 {
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@ -0,0 +1,32 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#include "dra72x.dtsi"
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/ {
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compatible = "ti,am5718", "ti,dra7";
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};
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/*
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* These modules are not present on AM5718
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*
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* ATL
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* VCP1, VCP2
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* MLB
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* ISS
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* USB3, USB4
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*/
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&usb3_tm {
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status = "disabled";
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};
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&usb4_tm {
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status = "disabled";
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};
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&atl_tm {
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status = "disabled";
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};
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@ -7,7 +7,7 @@
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*/
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/dts-v1/;
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#include "dra72x.dtsi"
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#include "am5718.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "dra7-mmc-iodelay.dtsi"
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@ -0,0 +1,33 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#include "dra74x.dtsi"
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/ {
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compatible = "ti,am5728", "ti,dra7";
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};
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/*
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* These modules are not present on AM5728
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*
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* EVE1, EVE2
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* ATL
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* VCP1, VCP2
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* MLB
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* ISS
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* USB3, USB4
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*/
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&usb3_tm {
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status = "disabled";
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};
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&usb4_tm {
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status = "disabled";
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};
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&atl_tm {
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status = "disabled";
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};
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@ -8,15 +8,14 @@
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/dts-v1/;
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#include "dra74x.dtsi"
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#include "am5728.dtsi"
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#include "dra7-mmc-iodelay.dtsi"
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#include "dra74x-mmc-iodelay.dtsi"
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#include "am572x-idk-common.dtsi"
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/ {
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model = "TI AM5728 IDK";
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compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74",
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"ti,dra7";
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compatible = "ti,am5728-idk", "ti,am5728", "ti,dra7";
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};
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&mmc1 {
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@ -0,0 +1,33 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#include "dra76x.dtsi"
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/ {
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compatible = "ti,am5748", "ti,dra762", "ti,dra7";
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};
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/*
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* These modules are not present on AM5748
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*
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* EVE1, EVE2
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* ATL
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* VCP1, VCP2
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* MLB
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* ISS
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* USB3, USB4
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*/
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&usb3_tm {
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status = "disabled";
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};
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&usb4_tm {
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status = "disabled";
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};
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&atl_tm {
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status = "disabled";
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};
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@ -6,14 +6,14 @@
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/dts-v1/;
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#include "dra76x.dtsi"
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#include "am5748.dtsi"
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#include "dra7-mmc-iodelay.dtsi"
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#include "dra76x-mmc-iodelay.dtsi"
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#include "am572x-idk-common.dtsi"
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/ {
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model = "TI AM5748 IDK";
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compatible = "ti,am5728-idk", "ti,dra762", "ti,dra7";
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compatible = "ti,am5748-idk", "ti,am5748", "ti,dra762", "ti,dra7";
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};
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&qspi {
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@ -7,7 +7,7 @@
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*/
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/dts-v1/;
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#include "dra74x.dtsi"
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#include "am5728.dtsi"
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#include "am57xx-commercial-grade.dtsi"
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#include "dra74x-mmc-iodelay.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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@ -13,7 +13,7 @@
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "dra74x.dtsi"
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#include "am5728.dtsi"
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/ {
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model = "CompuLab CL-SOM-AM57x";
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@ -2499,7 +2499,7 @@
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ranges = <0x0 0x3a000 0x1000>;
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};
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target-module@3c000 { /* 0x4843c000, ap 23 08.0 */
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atl_tm: target-module@3c000 { /* 0x4843c000, ap 23 08.0 */
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x3c000 0x4>;
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reg-names = "rev";
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@ -4099,7 +4099,7 @@
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};
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};
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target-module@100000 { /* 0x48900000, ap 85 04.0 */
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usb3_tm: target-module@100000 { /* 0x48900000, ap 85 04.0 */
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compatible = "ti,sysc-omap4", "ti,sysc";
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ti,hwmods = "usb_otg_ss3";
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reg = <0x100000 0x4>,
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@ -4148,7 +4148,7 @@
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};
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};
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target-module@140000 { /* 0x48940000, ap 75 3c.0 */
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usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */
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compatible = "ti,sysc-omap4", "ti,sysc";
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ti,hwmods = "usb_otg_ss4";
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reg = <0x140000 0x4>,
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@ -193,6 +193,7 @@
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ti,hwmods = "pcie1";
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phys = <&pcie1_phy>;
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phy-names = "pcie-phy0";
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ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie1_intc 1>,
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<0 0 0 2 &pcie1_intc 2>,
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phys = <&pcie1_phy>;
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phy-names = "pcie-phy0";
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ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
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ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
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status = "disabled";
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};
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};
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@ -48,7 +48,7 @@
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pinctrl-names = "default";
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pinctrl-0 = <&aic33_pins>;
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gpio-reset = <&gpio4 22 GPIO_ACTIVE_LOW>; /* gpio118 */
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reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; /* gpio118 */
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ai3x-gpio-func = <
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10 /* AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK */
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