bnx2x: Add and change some net_dev messages
Add and modify some net dev prints to improve error control Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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65a001bad1
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6d870c391e
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@ -1422,6 +1422,7 @@ static u8 bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
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}
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if (tmp & EMAC_MDIO_COMM_START_BUSY) {
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DP(NETIF_MSG_LINK, "write phy register failed\n");
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netdev_err(bp->dev, "MDC/MDIO access timeout\n");
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rc = -EFAULT;
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} else {
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/* data */
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@ -1442,6 +1443,7 @@ static u8 bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
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}
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if (tmp & EMAC_MDIO_COMM_START_BUSY) {
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DP(NETIF_MSG_LINK, "write phy register failed\n");
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netdev_err(bp->dev, "MDC/MDIO access timeout\n");
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rc = -EFAULT;
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}
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}
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@ -1489,7 +1491,7 @@ static u8 bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
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}
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if (val & EMAC_MDIO_COMM_START_BUSY) {
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DP(NETIF_MSG_LINK, "read phy register failed\n");
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netdev_err(bp->dev, "MDC/MDIO access timeout\n");
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*ret_val = 0;
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rc = -EFAULT;
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@ -1512,7 +1514,7 @@ static u8 bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
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}
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if (val & EMAC_MDIO_COMM_START_BUSY) {
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DP(NETIF_MSG_LINK, "read phy register failed\n");
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netdev_err(bp->dev, "MDC/MDIO access timeout\n");
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*ret_val = 0;
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rc = -EFAULT;
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}
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@ -1827,6 +1829,9 @@ static u8 bnx2x_reset_unicore(struct link_params *params,
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}
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}
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netdev_err(bp->dev, "Warning: PHY was not initialized,"
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" Port %d\n",
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params->port);
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DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
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return -EINVAL;
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@ -2846,7 +2851,8 @@ static u8 bnx2x_init_xgxs(struct bnx2x_phy *phy,
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}
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static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
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struct bnx2x_phy *phy)
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struct bnx2x_phy *phy,
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struct link_params *params)
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{
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u16 cnt, ctrl;
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/* Wait for soft reset to get cleared upto 1 sec */
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@ -2857,6 +2863,11 @@ static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
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break;
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msleep(1);
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}
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if (cnt == 1000)
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netdev_err(bp->dev, "Warning: PHY was not initialized,"
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" Port %d\n",
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params->port);
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DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
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return cnt;
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}
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@ -4402,7 +4413,7 @@ static u8 bnx2x_8705_config_init(struct bnx2x_phy *phy,
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/* HW reset */
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bnx2x_ext_phy_hw_reset(bp, params->port);
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bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
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bnx2x_wait_reset_complete(bp, phy);
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bnx2x_wait_reset_complete(bp, phy, params);
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bnx2x_cl45_write(bp, phy,
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MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
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@ -4797,7 +4808,7 @@ static u8 bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
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else
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vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
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netdev_info(bp->dev, "Warning: Unqualified SFP+ module detected,"
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netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected,"
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" Port %d from %s part number %s\n",
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params->port, vendor_name, vendor_pn);
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phy->flags |= FLAGS_SFP_NOT_APPROVED;
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@ -5142,7 +5153,7 @@ static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
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/* HW reset */
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bnx2x_ext_phy_hw_reset(bp, params->port);
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bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
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bnx2x_wait_reset_complete(bp, phy);
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bnx2x_wait_reset_complete(bp, phy, params);
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/* Wait until fw is loaded */
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for (cnt = 0; cnt < 100; cnt++) {
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@ -5305,7 +5316,7 @@ static u8 bnx2x_8726_config_init(struct bnx2x_phy *phy,
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MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
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bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
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bnx2x_wait_reset_complete(bp, phy);
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bnx2x_wait_reset_complete(bp, phy, params);
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bnx2x_8726_external_rom_boot(phy, params);
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@ -5495,7 +5506,7 @@ static u8 bnx2x_8727_config_init(struct bnx2x_phy *phy,
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struct bnx2x *bp = params->bp;
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/* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
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bnx2x_wait_reset_complete(bp, phy);
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bnx2x_wait_reset_complete(bp, phy, params);
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rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
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lasi_ctrl_val = 0x0004;
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@ -6117,7 +6128,7 @@ static u8 bnx2x_8481_config_init(struct bnx2x_phy *phy,
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/* HW reset */
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bnx2x_ext_phy_hw_reset(bp, params->port);
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bnx2x_wait_reset_complete(bp, phy);
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bnx2x_wait_reset_complete(bp, phy, params);
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bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
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return bnx2x_848xx_cmn_config_init(phy, params, vars);
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@ -6144,7 +6155,7 @@ static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy,
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bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
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MISC_REGISTERS_GPIO_OUTPUT_HIGH,
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port);
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bnx2x_wait_reset_complete(bp, phy);
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bnx2x_wait_reset_complete(bp, phy, params);
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/* Wait for GPHY to come out of reset */
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msleep(50);
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/*
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@ -6544,7 +6555,7 @@ static u8 bnx2x_7101_config_init(struct bnx2x_phy *phy,
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MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
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/* HW reset */
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bnx2x_ext_phy_hw_reset(bp, params->port);
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bnx2x_wait_reset_complete(bp, phy);
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bnx2x_wait_reset_complete(bp, phy, params);
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bnx2x_cl45_write(bp, phy,
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MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x1);
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@ -8000,6 +8011,10 @@ static u8 bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
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break;
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}
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if (rc != 0)
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netdev_err(bp->dev, "Warning: PHY was not initialized,"
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" Port %d\n",
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0);
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return rc;
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}
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