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pinctrl: renesas: r8a77980: Add support for AVB/GE power-sources 

Add support for configuring the I/O voltage levels of the Ethernet AVB
and Gigabit Ethernet pins on the R-Car V3H SoC.  "PIN_VDDQ_AVB" and
"PIN_VDDQ_GE" can be configured for 2.5V or 3.3V operation.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/3c26c4f3735a6d071685c507c065172e63af5d70.1678271030.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2023-03-08 11:42:41 +01:00
parent a7bebdc590
commit 6cd853a453
1 changed files with 28 additions and 11 deletions
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39
drivers/pinctrl/renesas/pfc-r8a77980.c
View File

@ -35,7 +35,9 @@
PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(VDDQ_AVB, "VDDQ_AVB", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33), \
PIN_NOGP_CFG(VDDQ_GE, "VDDQ_GE", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
/* /*
* F_() : just information * F_() : just information
@ -2837,24 +2839,39 @@ static int r8a77980_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{ {
int bit = pin & 0x1f; int bit = pin & 0x1f;
*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; switch (pin) {
if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21)) case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 21):
*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
return bit; return bit;
else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
case RCAR_GP_PIN(2, 0) ... RCAR_GP_PIN(2, 9):
*pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
return bit + 22; return bit + 22;
*pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg; case RCAR_GP_PIN(2, 10) ... RCAR_GP_PIN(2, 16):
if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16)) *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
return bit - 10; return bit - 10;
if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) ||
(pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))) case RCAR_GP_PIN(2, 17) ... RCAR_GP_PIN(2, 24):
case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 16):
*pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
return bit + 7; return bit + 7;
*pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg; case RCAR_GP_PIN(2, 25) ... RCAR_GP_PIN(2, 29):
if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29)) *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
return pin - 25; return pin - 25;
return -EINVAL; case PIN_VDDQ_AVB:
*pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg;
return 0;
case PIN_VDDQ_GE:
*pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg;
return 1;
default:
return -EINVAL;
}
} }
static const struct pinmux_bias_reg pinmux_bias_regs[] = { static const struct pinmux_bias_reg pinmux_bias_regs[] = {