drm/i915: rename raw reg access functions
They now work on uncore, so use raw_uncore_ prefix. Also move them to uncore.h Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190325214940.23632-2-daniele.ceraolospurio@intel.com
This commit is contained in:
Daniele Ceraolo Spurio
Chris Wilson
parent
077973c8c3
commit
6cc5ca7688
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@ -3518,32 +3518,6 @@ static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
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#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
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#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
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#define __raw_read(x, s) \
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static inline uint##x##_t __raw_i915_read##x(const struct intel_uncore *uncore, \
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i915_reg_t reg) \
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{ \
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return read##s(uncore->regs + i915_mmio_reg_offset(reg)); \
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}
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#define __raw_write(x, s) \
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static inline void __raw_i915_write##x(const struct intel_uncore *uncore, \
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i915_reg_t reg, uint##x##_t val) \
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{ \
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write##s(val, uncore->regs + i915_mmio_reg_offset(reg)); \
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}
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__raw_read(8, b)
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__raw_read(16, w)
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__raw_read(32, l)
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__raw_read(64, q)
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__raw_write(8, b)
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__raw_write(16, w)
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__raw_write(32, l)
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__raw_write(64, q)
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#undef __raw_read
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#undef __raw_write
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/* These are untraced mmio-accessors that are only valid to be used inside
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* critical sections, such as inside IRQ handlers, where forcewake is explicitly
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* controlled.
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@ -3570,9 +3544,9 @@ __raw_write(64, q)
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* therefore generally be serialised, by either the dev_priv->uncore.lock or
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* a more localised lock guarding all access to that bank of registers.
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*/
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#define I915_READ_FW(reg__) __raw_i915_read32(&dev_priv->uncore, (reg__))
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#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(&dev_priv->uncore, (reg__), (val__))
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#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(&dev_priv->uncore, (reg__), (val__))
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#define I915_READ_FW(reg__) __raw_uncore_read32(&dev_priv->uncore, (reg__))
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#define I915_WRITE_FW(reg__, val__) __raw_uncore_write32(&dev_priv->uncore, (reg__), (val__))
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#define I915_WRITE64_FW(reg__, val__) __raw_uncore_write64(&dev_priv->uncore, (reg__), (val__))
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#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
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/* "Broadcast RGB" property */
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@ -66,17 +66,17 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
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BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
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magic = __raw_i915_read64(uncore, vgtif_reg(magic));
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magic = __raw_uncore_read64(uncore, vgtif_reg(magic));
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if (magic != VGT_MAGIC)
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return;
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version_major = __raw_i915_read16(uncore, vgtif_reg(version_major));
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version_major = __raw_uncore_read16(uncore, vgtif_reg(version_major));
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if (version_major < VGT_VERSION_MAJOR) {
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DRM_INFO("VGT interface version mismatch!\n");
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return;
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}
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dev_priv->vgpu.caps = __raw_i915_read32(uncore, vgtif_reg(vgt_caps));
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dev_priv->vgpu.caps = __raw_uncore_read32(uncore, vgtif_reg(vgt_caps));
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dev_priv->vgpu.active = true;
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DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
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@ -31,7 +31,7 @@
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#define FORCEWAKE_ACK_TIMEOUT_MS 50
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#define GT_FIFO_TIMEOUT_MS 10
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#define __raw_posting_read(uncore__, reg__) (void)__raw_i915_read32((uncore__), (reg__))
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#define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
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static const char * const forcewake_domain_names[] = {
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"render",
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@ -279,7 +279,7 @@ static inline u32 gt_thread_status(struct intel_uncore *uncore)
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{
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u32 val;
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val = __raw_i915_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
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val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG);
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val &= GEN6_GT_THREAD_STATUS_CORE_MASK;
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return val;
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@ -306,7 +306,7 @@ static void fw_domains_get_with_thread_status(struct intel_uncore *uncore,
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static inline u32 fifo_free_entries(struct intel_uncore *uncore)
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{
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u32 count = __raw_i915_read32(uncore, GTFIFOCTL);
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u32 count = __raw_uncore_read32(uncore, GTFIFOCTL);
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return count & GT_FIFO_FREE_ENTRIES_MASK;
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}
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@ -451,8 +451,8 @@ static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv)
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if (IS_HASWELL(dev_priv) ||
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IS_BROADWELL(dev_priv) ||
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INTEL_GEN(dev_priv) >= 9) {
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dev_priv->edram_cap = __raw_i915_read32(&dev_priv->uncore,
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HSW_EDRAM_CAP);
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dev_priv->edram_cap = __raw_uncore_read32(&dev_priv->uncore,
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HSW_EDRAM_CAP);
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/* NB: We can't write IDICR yet because we do not have gt funcs
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* set up */
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@ -470,11 +470,11 @@ fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore)
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{
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u32 dbg;
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dbg = __raw_i915_read32(uncore, FPGA_DBG);
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dbg = __raw_uncore_read32(uncore, FPGA_DBG);
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if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))
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return false;
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__raw_i915_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
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__raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
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return true;
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}
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@ -484,11 +484,11 @@ vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore)
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{
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u32 cer;
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cer = __raw_i915_read32(uncore, CLAIM_ER);
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cer = __raw_uncore_read32(uncore, CLAIM_ER);
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if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))
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return false;
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__raw_i915_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
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__raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR);
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return true;
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}
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@ -498,11 +498,11 @@ gen6_check_for_fifo_debug(struct intel_uncore *uncore)
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{
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u32 fifodbg;
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fifodbg = __raw_i915_read32(uncore, GTFIFODBG);
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fifodbg = __raw_uncore_read32(uncore, GTFIFODBG);
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if (unlikely(fifodbg)) {
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DRM_DEBUG_DRIVER("GTFIFODBG = 0x08%x\n", fifodbg);
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__raw_i915_write32(uncore, GTFIFODBG, fifodbg);
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__raw_uncore_write32(uncore, GTFIFODBG, fifodbg);
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}
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return fifodbg;
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@ -537,10 +537,10 @@ static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
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/* WaDisableShadowRegForCpd:chv */
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if (IS_CHERRYVIEW(i915)) {
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__raw_i915_write32(uncore, GTFIFOCTL,
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__raw_i915_read32(uncore, GTFIFOCTL) |
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GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
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GT_FIFO_CTL_RC6_POLICY_STALL);
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__raw_uncore_write32(uncore, GTFIFOCTL,
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__raw_uncore_read32(uncore, GTFIFOCTL) |
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GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
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GT_FIFO_CTL_RC6_POLICY_STALL);
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}
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iosf_mbi_punit_acquire();
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@ -1068,7 +1068,7 @@ ilk_dummy_write(struct intel_uncore *uncore)
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/* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
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* the chip from rc6 before touching it for real. MI_MODE is masked,
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* hence harmless to write 0 into. */
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__raw_i915_write32(uncore, MI_MODE, 0);
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__raw_uncore_write32(uncore, MI_MODE, 0);
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}
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static void
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@ -1110,7 +1110,7 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv,
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static u##x \
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gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
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GEN2_READ_HEADER(x); \
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val = __raw_i915_read##x(uncore, reg); \
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val = __raw_uncore_read##x(uncore, reg); \
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GEN2_READ_FOOTER; \
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}
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@ -1119,7 +1119,7 @@ static u##x \
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gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
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GEN2_READ_HEADER(x); \
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ilk_dummy_write(uncore); \
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val = __raw_i915_read##x(uncore, reg); \
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val = __raw_uncore_read##x(uncore, reg); \
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GEN2_READ_FOOTER; \
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}
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@ -1189,7 +1189,7 @@ func##_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) {
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fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \
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if (fw_engine) \
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__force_wake_auto(uncore, fw_engine); \
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val = __raw_i915_read##x(uncore, reg); \
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val = __raw_uncore_read##x(uncore, reg); \
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GEN6_READ_FOOTER; \
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}
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#define __gen6_read(x) __gen_read(gen6, x)
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@ -1226,7 +1226,7 @@ __gen6_read(64)
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static void \
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gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
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GEN2_WRITE_HEADER; \
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__raw_i915_write##x(uncore, reg, val); \
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__raw_uncore_write##x(uncore, reg, val); \
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GEN2_WRITE_FOOTER; \
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}
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@ -1235,7 +1235,7 @@ static void \
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gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
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GEN2_WRITE_HEADER; \
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ilk_dummy_write(uncore); \
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__raw_i915_write##x(uncore, reg, val); \
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__raw_uncore_write##x(uncore, reg, val); \
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GEN2_WRITE_FOOTER; \
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}
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@ -1271,7 +1271,7 @@ gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool
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GEN6_WRITE_HEADER; \
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if (NEEDS_FORCE_WAKE(offset)) \
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__gen6_gt_wait_for_fifo(uncore); \
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__raw_i915_write##x(uncore, reg, val); \
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__raw_uncore_write##x(uncore, reg, val); \
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GEN6_WRITE_FOOTER; \
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}
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@ -1283,7 +1283,7 @@ func##_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, boo
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fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \
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if (fw_engine) \
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__force_wake_auto(uncore, fw_engine); \
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__raw_i915_write##x(uncore, reg, val); \
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__raw_uncore_write##x(uncore, reg, val); \
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GEN6_WRITE_FOOTER; \
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}
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#define __gen8_write(x) __gen_write(gen8, x)
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@ -1470,7 +1470,7 @@ static void intel_uncore_fw_domains_init(struct intel_uncore *uncore)
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* before the ecobus check.
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*/
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__raw_i915_write32(uncore, FORCEWAKE, 0);
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__raw_uncore_write32(uncore, FORCEWAKE, 0);
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__raw_posting_read(uncore, ECOBUS);
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fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
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@ -1478,7 +1478,7 @@ static void intel_uncore_fw_domains_init(struct intel_uncore *uncore)
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spin_lock_irq(&uncore->lock);
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fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER);
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ecobus = __raw_i915_read32(uncore, ECOBUS);
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ecobus = __raw_uncore_read32(uncore, ECOBUS);
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fw_domains_put(uncore, FORCEWAKE_RENDER);
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spin_unlock_irq(&uncore->lock);
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@ -215,6 +215,33 @@ int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
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2, timeout_ms, NULL);
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}
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/* register access functions */
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#define __raw_read(x__, s__) \
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static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, \
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i915_reg_t reg) \
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{ \
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return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
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}
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#define __raw_write(x__, s__) \
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static inline void __raw_uncore_write##x__(const struct intel_uncore *uncore, \
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i915_reg_t reg, u##x__ val) \
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{ \
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write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
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}
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__raw_read(8, b)
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__raw_read(16, w)
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__raw_read(32, l)
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__raw_read(64, q)
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__raw_write(8, b)
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__raw_write(16, w)
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__raw_write(32, l)
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__raw_write(64, q)
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#undef __raw_read
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#undef __raw_write
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#define raw_reg_read(base, reg) \
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readl(base + i915_mmio_reg_offset(reg))
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#define raw_reg_write(base, reg, value) \
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