ARM: edma: Add DT and runtime PM support to the private EDMA API
Adds support for parsing the TI EDMA DT data into the required EDMA private API platform data. Enables runtime PM support to initialize the EDMA hwmod. Enables build on OMAP. Changes by Joel: * Setup default one-to-one mapping for queue_priority and queue_tc mapping as discussed in [1]. * Split out xbar stuff to separate patch. [1] * Dropped unused DT helper to convert to array * Fixed dangling pointer issue with Sekhar's changes [1] https://patchwork.kernel.org/patch/2226761/ Signed-off-by: Matt Porter <mporter@ti.com> [nsekhar@ti.com: fix checkpatch errors, build breakages. Introduce edma_setup_info_from_dt() as part of that effort] Signed-off-by: Joel A Fernandes <joelagnel@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This commit is contained in:
Matt Porter
Sekhar Nori
parent
bf3156dde3
commit
6cba435506
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@ -25,6 +25,13 @@
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/edma.h>
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#include <linux/err.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_dma.h>
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#include <linux/of_irq.h>
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#include <linux/pm_runtime.h>
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#include <linux/platform_data/edma.h>
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@ -1369,13 +1376,110 @@ void edma_clear_event(unsigned channel)
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}
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EXPORT_SYMBOL(edma_clear_event);
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/*-----------------------------------------------------------------------*/
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#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES)
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static int __init edma_probe(struct platform_device *pdev)
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static int edma_of_parse_dt(struct device *dev,
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struct device_node *node,
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struct edma_soc_info *pdata)
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{
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int ret = 0, i;
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u32 value;
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struct edma_rsv_info *rsv_info;
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s8 (*queue_tc_map)[2], (*queue_priority_map)[2];
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memset(pdata, 0, sizeof(struct edma_soc_info));
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ret = of_property_read_u32(node, "dma-channels", &value);
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if (ret < 0)
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return ret;
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pdata->n_channel = value;
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ret = of_property_read_u32(node, "ti,edma-regions", &value);
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if (ret < 0)
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return ret;
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pdata->n_region = value;
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ret = of_property_read_u32(node, "ti,edma-slots", &value);
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if (ret < 0)
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return ret;
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pdata->n_slot = value;
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pdata->n_cc = 1;
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rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
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if (!rsv_info)
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return -ENOMEM;
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pdata->rsv = rsv_info;
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queue_tc_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL);
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if (!queue_tc_map)
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return -ENOMEM;
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for (i = 0; i < 3; i++) {
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queue_tc_map[i][0] = i;
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queue_tc_map[i][1] = i;
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}
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queue_tc_map[i][0] = -1;
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queue_tc_map[i][1] = -1;
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pdata->queue_tc_mapping = queue_tc_map;
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queue_priority_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL);
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if (!queue_priority_map)
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return -ENOMEM;
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for (i = 0; i < 3; i++) {
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queue_priority_map[i][0] = i;
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queue_priority_map[i][1] = i;
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}
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queue_priority_map[i][0] = -1;
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queue_priority_map[i][1] = -1;
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pdata->queue_priority_mapping = queue_priority_map;
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pdata->default_queue = 0;
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return ret;
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}
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static struct of_dma_filter_info edma_filter_info = {
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.filter_fn = edma_filter_fn,
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};
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static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
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struct device_node *node)
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{
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struct edma_soc_info *info;
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int ret;
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info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
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if (!info)
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return ERR_PTR(-ENOMEM);
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ret = edma_of_parse_dt(dev, node, info);
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if (ret)
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return ERR_PTR(ret);
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dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
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of_dma_controller_register(dev->of_node, of_dma_simple_xlate,
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&edma_filter_info);
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return info;
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}
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#else
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static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
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struct device_node *node)
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{
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return ERR_PTR(-ENOSYS);
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}
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#endif
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static int edma_probe(struct platform_device *pdev)
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{
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struct edma_soc_info **info = pdev->dev.platform_data;
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const s8 (*queue_priority_mapping)[2];
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const s8 (*queue_tc_mapping)[2];
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struct edma_soc_info *ninfo[EDMA_MAX_CC] = {NULL};
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s8 (*queue_priority_mapping)[2];
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s8 (*queue_tc_mapping)[2];
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int i, j, off, ln, found = 0;
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int status = -1;
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const s16 (*rsv_chans)[2];
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@ -1383,17 +1487,56 @@ static int __init edma_probe(struct platform_device *pdev)
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int irq[EDMA_MAX_CC] = {0, 0};
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int err_irq[EDMA_MAX_CC] = {0, 0};
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struct resource *r[EDMA_MAX_CC] = {NULL};
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struct resource res[EDMA_MAX_CC];
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char res_name[10];
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char irq_name[10];
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struct device_node *node = pdev->dev.of_node;
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struct device *dev = &pdev->dev;
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int ret;
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if (node) {
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/* Check if this is a second instance registered */
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if (arch_num_cc) {
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dev_err(dev, "only one EDMA instance is supported via DT\n");
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return -ENODEV;
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}
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ninfo[0] = edma_setup_info_from_dt(dev, node);
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if (IS_ERR(ninfo[0])) {
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dev_err(dev, "failed to get DT data\n");
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return PTR_ERR(ninfo[0]);
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}
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info = ninfo;
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}
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if (!info)
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return -ENODEV;
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pm_runtime_enable(dev);
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ret = pm_runtime_get_sync(dev);
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if (ret < 0) {
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dev_err(dev, "pm_runtime_get_sync() failed\n");
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return ret;
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}
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for (j = 0; j < EDMA_MAX_CC; j++) {
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sprintf(res_name, "edma_cc%d", j);
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r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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if (!info[j]) {
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if (!found)
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return -ENODEV;
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break;
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}
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if (node) {
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ret = of_address_to_resource(node, j, &res[j]);
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if (!ret)
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r[j] = &res[j];
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} else {
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sprintf(res_name, "edma_cc%d", j);
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r[j] = platform_get_resource_byname(pdev,
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IORESOURCE_MEM,
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res_name);
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if (!r[j] || !info[j]) {
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}
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if (!r[j]) {
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if (found)
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break;
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else
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@ -1440,7 +1583,7 @@ static int __init edma_probe(struct platform_device *pdev)
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off = rsv_chans[i][0];
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ln = rsv_chans[i][1];
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clear_bits(off, ln,
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edma_cc[j]->edma_unused);
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edma_cc[j]->edma_unused);
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}
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}
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@ -1456,8 +1599,13 @@ static int __init edma_probe(struct platform_device *pdev)
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}
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}
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sprintf(irq_name, "edma%d", j);
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irq[j] = platform_get_irq_byname(pdev, irq_name);
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if (node) {
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irq[j] = irq_of_parse_and_map(node, 0);
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} else {
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sprintf(irq_name, "edma%d", j);
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irq[j] = platform_get_irq_byname(pdev, irq_name);
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}
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edma_cc[j]->irq_res_start = irq[j];
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status = devm_request_irq(&pdev->dev, irq[j],
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dma_irq_handler, 0, "edma",
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@ -1469,8 +1617,12 @@ static int __init edma_probe(struct platform_device *pdev)
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return status;
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}
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sprintf(irq_name, "edma%d_err", j);
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err_irq[j] = platform_get_irq_byname(pdev, irq_name);
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if (node) {
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err_irq[j] = irq_of_parse_and_map(node, 2);
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} else {
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sprintf(irq_name, "edma%d_err", j);
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err_irq[j] = platform_get_irq_byname(pdev, irq_name);
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}
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edma_cc[j]->irq_res_end = err_irq[j];
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status = devm_request_irq(&pdev->dev, err_irq[j],
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dma_ccerr_handler, 0,
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@ -1516,9 +1668,17 @@ static int __init edma_probe(struct platform_device *pdev)
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return 0;
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}
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static const struct of_device_id edma_of_ids[] = {
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{ .compatible = "ti,edma3", },
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{}
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};
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static struct platform_driver edma_driver = {
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.driver.name = "edma",
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.driver = {
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.name = "edma",
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.of_match_table = edma_of_ids,
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},
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.probe = edma_probe,
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};
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static int __init edma_init(void)
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@ -105,27 +105,27 @@ struct platform_device da8xx_serial_device = {
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},
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};
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static const s8 da8xx_queue_tc_mapping[][2] = {
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static s8 da8xx_queue_tc_mapping[][2] = {
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/* {event queue no, TC no} */
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{0, 0},
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{1, 1},
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{-1, -1}
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};
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static const s8 da8xx_queue_priority_mapping[][2] = {
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static s8 da8xx_queue_priority_mapping[][2] = {
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/* {event queue no, Priority} */
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{0, 3},
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{1, 7},
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{-1, -1}
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};
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static const s8 da850_queue_tc_mapping[][2] = {
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static s8 da850_queue_tc_mapping[][2] = {
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/* {event queue no, TC no} */
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{0, 0},
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{-1, -1}
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};
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static const s8 da850_queue_priority_mapping[][2] = {
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static s8 da850_queue_priority_mapping[][2] = {
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/* {event queue no, Priority} */
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{0, 3},
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{-1, -1}
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@ -58,14 +58,14 @@
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#define TNETV107X_DMACH_SDIO1_RX 28
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#define TNETV107X_DMACH_SDIO1_TX 29
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static const s8 edma_tc_mapping[][2] = {
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static s8 edma_tc_mapping[][2] = {
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/* event queue no TC no */
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{ 0, 0 },
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{ 1, 1 },
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{ -1, -1 }
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};
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static const s8 edma_priority_mapping[][2] = {
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static s8 edma_priority_mapping[][2] = {
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/* event queue no Prio */
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{ 0, 3 },
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{ 1, 7 },
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@ -569,7 +569,7 @@ static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
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/*----------------------------------------------------------------------*/
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static const s8
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static s8
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queue_tc_mapping[][2] = {
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/* {event queue no, TC no} */
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{0, 0},
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@ -577,7 +577,7 @@ queue_tc_mapping[][2] = {
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{-1, -1},
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};
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static const s8
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static s8
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queue_priority_mapping[][2] = {
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/* {event queue no, Priority} */
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{0, 3},
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@ -826,7 +826,7 @@ static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
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};
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/* Four Transfer Controllers on DM365 */
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static const s8
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static s8
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dm365_queue_tc_mapping[][2] = {
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/* {event queue no, TC no} */
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{0, 0},
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@ -836,7 +836,7 @@ dm365_queue_tc_mapping[][2] = {
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{-1, -1},
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};
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static const s8
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static s8
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dm365_queue_priority_mapping[][2] = {
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/* {event queue no, Priority} */
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{0, 7},
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@ -497,7 +497,7 @@ static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
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/*----------------------------------------------------------------------*/
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static const s8
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static s8
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queue_tc_mapping[][2] = {
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/* {event queue no, TC no} */
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{0, 0},
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@ -505,7 +505,7 @@ queue_tc_mapping[][2] = {
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{-1, -1},
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};
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static const s8
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static s8
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queue_priority_mapping[][2] = {
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/* {event queue no, Priority} */
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{0, 3},
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@ -531,7 +531,7 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
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/*----------------------------------------------------------------------*/
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/* Four Transfer Controllers on DM646x */
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static const s8
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static s8
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dm646x_queue_tc_mapping[][2] = {
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/* {event queue no, TC no} */
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{0, 0},
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@ -541,7 +541,7 @@ dm646x_queue_tc_mapping[][2] = {
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{-1, -1},
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};
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static const s8
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static s8
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dm646x_queue_priority_mapping[][2] = {
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/* {event queue no, Priority} */
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{0, 4},
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@ -175,8 +175,8 @@ struct edma_soc_info {
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/* Resource reservation for other cores */
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struct edma_rsv_info *rsv;
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const s8 (*queue_tc_mapping)[2];
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const s8 (*queue_priority_mapping)[2];
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s8 (*queue_tc_mapping)[2];
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s8 (*queue_priority_mapping)[2];
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};
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#endif
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