arm64: perf: Allow standard PMUv3 events to be extended by the CPU type
Rather than continue adding CPU-specific event maps, instead look up by default in the PMUv3 event map and only fallback to the CPU-specific maps if either the event isn't described by PMUv3, or it is described but the PMCEID registers say that it is unsupported by the current CPU. Signed-off-by: Will Deacon <will.deacon@arm.com>
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@ -921,7 +921,13 @@ static void armv8pmu_reset(void *info)
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ARMV8_PMU_PMCR_LC);
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}
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static int armv8_pmuv3_map_event(struct perf_event *event)
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static int __armv8_pmuv3_map_event(struct perf_event *event,
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const unsigned (*extra_event_map)
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[PERF_COUNT_HW_MAX],
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const unsigned (*extra_cache_map)
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX])
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{
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int hw_event_id;
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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@ -929,44 +935,44 @@ static int armv8_pmuv3_map_event(struct perf_event *event)
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hw_event_id = armpmu_map_event(event, &armv8_pmuv3_perf_map,
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&armv8_pmuv3_perf_cache_map,
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ARMV8_PMU_EVTYPE_EVENT);
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if (hw_event_id < 0)
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return hw_event_id;
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/* disable micro/arch events not supported by this PMU */
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if ((hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS) &&
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!test_bit(hw_event_id, armpmu->pmceid_bitmap)) {
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return -EOPNOTSUPP;
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/* Onl expose micro/arch events supported by this PMU */
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if ((hw_event_id > 0) && (hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS)
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&& test_bit(hw_event_id, armpmu->pmceid_bitmap)) {
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return hw_event_id;
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}
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return hw_event_id;
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return armpmu_map_event(event, extra_event_map, extra_cache_map,
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ARMV8_PMU_EVTYPE_EVENT);
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}
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static int armv8_pmuv3_map_event(struct perf_event *event)
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{
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return __armv8_pmuv3_map_event(event, NULL, NULL);
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}
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static int armv8_a53_map_event(struct perf_event *event)
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{
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return armpmu_map_event(event, &armv8_a53_perf_map,
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&armv8_a53_perf_cache_map,
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ARMV8_PMU_EVTYPE_EVENT);
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return __armv8_pmuv3_map_event(event, &armv8_a53_perf_map,
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&armv8_a53_perf_cache_map);
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}
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static int armv8_a57_map_event(struct perf_event *event)
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{
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return armpmu_map_event(event, &armv8_a57_perf_map,
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&armv8_a57_perf_cache_map,
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ARMV8_PMU_EVTYPE_EVENT);
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return __armv8_pmuv3_map_event(event, &armv8_a57_perf_map,
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&armv8_a57_perf_cache_map);
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}
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static int armv8_thunder_map_event(struct perf_event *event)
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{
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return armpmu_map_event(event, &armv8_thunder_perf_map,
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&armv8_thunder_perf_cache_map,
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ARMV8_PMU_EVTYPE_EVENT);
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return __armv8_pmuv3_map_event(event, &armv8_thunder_perf_map,
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&armv8_thunder_perf_cache_map);
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}
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static int armv8_vulcan_map_event(struct perf_event *event)
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{
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return armpmu_map_event(event, &armv8_vulcan_perf_map,
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&armv8_vulcan_perf_cache_map,
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ARMV8_PMU_EVTYPE_EVENT);
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return __armv8_pmuv3_map_event(event, &armv8_vulcan_perf_map,
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&armv8_vulcan_perf_cache_map);
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}
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struct armv8pmu_probe_info {
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@ -47,6 +47,9 @@ armpmu_map_cache_event(const unsigned (*cache_map)
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if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
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return -EINVAL;
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if (!cache_map)
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return -ENOENT;
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ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
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if (ret == CACHE_OP_UNSUPPORTED)
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@ -63,6 +66,9 @@ armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
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if (config >= PERF_COUNT_HW_MAX)
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return -EINVAL;
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if (!event_map)
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return -ENOENT;
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mapping = (*event_map)[config];
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return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
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}
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