rtc: ds1307: add clock provider support for DS3231
DS3231 has programmable square-wave output signal. This enables to use this feature as a clock provider of common clock framework. Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Reviewed-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
This commit is contained in:
Akinobu Mita
Alexandre Belloni
parent
f3937549a9
commit
6c6ff145b3
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@ -0,0 +1,37 @@
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* Maxim DS3231 Real Time Clock
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Required properties:
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see: Documentation/devicetree/bindings/i2c/trivial-devices.txt
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Optional property:
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- #clock-cells: Should be 1.
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- clock-output-names:
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overwrite the default clock names "ds3231_clk_sqw" and "ds3231_clk_32khz".
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. Following indices are allowed:
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- 0: square-wave output on the SQW pin
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- 1: square-wave output on the 32kHz pin
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- interrupts: rtc alarm/event interrupt. When this property is selected,
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clock on the SQW pin cannot be used.
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Example:
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ds3231: ds3231@51 {
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compatible = "maxim,ds3231";
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reg = <0x68>;
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#clock-cells = <1>;
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};
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device1 {
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...
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clocks = <&ds3231 0>;
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...
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};
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device2 {
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...
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clocks = <&ds3231 1>;
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...
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};
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@ -21,6 +21,7 @@
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#include <linux/string.h>
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#include <linux/hwmon.h>
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#include <linux/hwmon-sysfs.h>
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#include <linux/clk-provider.h>
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/*
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* We can't determine type by probing, but if we expect pre-Linux code
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@ -91,6 +92,7 @@ enum ds_type {
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# define DS1340_BIT_OSF 0x80
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#define DS1337_REG_STATUS 0x0f
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# define DS1337_BIT_OSF 0x80
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# define DS3231_BIT_EN32KHZ 0x08
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# define DS1337_BIT_A2I 0x02
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# define DS1337_BIT_A1I 0x01
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#define DS1339_REG_ALARM1_SECS 0x07
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@ -120,6 +122,9 @@ struct ds1307 {
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u8 length, u8 *values);
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s32 (*write_block_data)(const struct i2c_client *client, u8 command,
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u8 length, const u8 *values);
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#ifdef CONFIG_COMMON_CLK
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struct clk_hw clks[2];
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#endif
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};
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struct chip_desc {
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@ -926,7 +931,295 @@ static void ds1307_hwmon_register(struct ds1307 *ds1307)
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{
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}
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#endif
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#endif /* CONFIG_RTC_DRV_DS1307_HWMON */
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/*----------------------------------------------------------------------*/
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/*
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* Square-wave output support for DS3231
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* Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
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*/
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#ifdef CONFIG_COMMON_CLK
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enum {
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DS3231_CLK_SQW = 0,
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DS3231_CLK_32KHZ,
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};
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#define clk_sqw_to_ds1307(clk) \
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container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
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#define clk_32khz_to_ds1307(clk) \
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container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
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static int ds3231_clk_sqw_rates[] = {
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1,
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1024,
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4096,
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8192,
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};
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static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
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{
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struct i2c_client *client = ds1307->client;
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struct mutex *lock = &ds1307->rtc->ops_lock;
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int control;
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int ret;
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mutex_lock(lock);
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control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
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if (control < 0) {
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ret = control;
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goto out;
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}
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control &= ~mask;
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control |= value;
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ret = i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control);
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out:
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mutex_unlock(lock);
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return ret;
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}
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static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
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int control;
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int rate_sel = 0;
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control = i2c_smbus_read_byte_data(ds1307->client, DS1337_REG_CONTROL);
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if (control < 0)
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return control;
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if (control & DS1337_BIT_RS1)
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rate_sel += 1;
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if (control & DS1337_BIT_RS2)
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rate_sel += 2;
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return ds3231_clk_sqw_rates[rate_sel];
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}
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static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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int i;
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for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
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if (ds3231_clk_sqw_rates[i] <= rate)
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return ds3231_clk_sqw_rates[i];
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}
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return 0;
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}
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static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
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int control = 0;
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int rate_sel;
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for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
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rate_sel++) {
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if (ds3231_clk_sqw_rates[rate_sel] == rate)
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break;
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}
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if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
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return -EINVAL;
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if (rate_sel & 1)
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control |= DS1337_BIT_RS1;
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if (rate_sel & 2)
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control |= DS1337_BIT_RS2;
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return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
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control);
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}
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static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
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{
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struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
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return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
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}
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static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
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{
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struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
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ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
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}
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static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
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{
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struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
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int control;
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control = i2c_smbus_read_byte_data(ds1307->client, DS1337_REG_CONTROL);
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if (control < 0)
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return control;
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return !(control & DS1337_BIT_INTCN);
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}
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static const struct clk_ops ds3231_clk_sqw_ops = {
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.prepare = ds3231_clk_sqw_prepare,
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.unprepare = ds3231_clk_sqw_unprepare,
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.is_prepared = ds3231_clk_sqw_is_prepared,
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.recalc_rate = ds3231_clk_sqw_recalc_rate,
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.round_rate = ds3231_clk_sqw_round_rate,
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.set_rate = ds3231_clk_sqw_set_rate,
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};
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static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return 32768;
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}
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static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
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{
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struct i2c_client *client = ds1307->client;
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struct mutex *lock = &ds1307->rtc->ops_lock;
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int status;
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int ret;
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mutex_lock(lock);
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status = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS);
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if (status < 0) {
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ret = status;
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goto out;
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}
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if (enable)
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status |= DS3231_BIT_EN32KHZ;
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else
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status &= ~DS3231_BIT_EN32KHZ;
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ret = i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, status);
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out:
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mutex_unlock(lock);
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return ret;
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}
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static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
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{
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struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
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return ds3231_clk_32khz_control(ds1307, true);
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}
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static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
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{
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struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
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ds3231_clk_32khz_control(ds1307, false);
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}
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static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
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{
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struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
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int status;
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status = i2c_smbus_read_byte_data(ds1307->client, DS1337_REG_STATUS);
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if (status < 0)
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return status;
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return !!(status & DS3231_BIT_EN32KHZ);
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}
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static const struct clk_ops ds3231_clk_32khz_ops = {
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.prepare = ds3231_clk_32khz_prepare,
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.unprepare = ds3231_clk_32khz_unprepare,
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.is_prepared = ds3231_clk_32khz_is_prepared,
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.recalc_rate = ds3231_clk_32khz_recalc_rate,
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};
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static struct clk_init_data ds3231_clks_init[] = {
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[DS3231_CLK_SQW] = {
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.name = "ds3231_clk_sqw",
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.ops = &ds3231_clk_sqw_ops,
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.flags = CLK_IS_ROOT,
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},
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[DS3231_CLK_32KHZ] = {
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.name = "ds3231_clk_32khz",
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.ops = &ds3231_clk_32khz_ops,
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.flags = CLK_IS_ROOT,
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},
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};
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static int ds3231_clks_register(struct ds1307 *ds1307)
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{
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struct i2c_client *client = ds1307->client;
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struct device_node *node = client->dev.of_node;
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struct clk_onecell_data *onecell;
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int i;
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onecell = devm_kzalloc(&client->dev, sizeof(*onecell), GFP_KERNEL);
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if (!onecell)
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return -ENOMEM;
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onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
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onecell->clks = devm_kcalloc(&client->dev, onecell->clk_num,
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sizeof(onecell->clks[0]), GFP_KERNEL);
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if (!onecell->clks)
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return -ENOMEM;
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for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
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struct clk_init_data init = ds3231_clks_init[i];
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/*
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* Interrupt signal due to alarm conditions and square-wave
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* output share same pin, so don't initialize both.
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*/
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if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
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continue;
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/* optional override of the clockname */
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of_property_read_string_index(node, "clock-output-names", i,
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&init.name);
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ds1307->clks[i].init = &init;
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onecell->clks[i] = devm_clk_register(&client->dev,
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&ds1307->clks[i]);
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if (IS_ERR(onecell->clks[i]))
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return PTR_ERR(onecell->clks[i]);
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}
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if (!node)
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return 0;
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of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
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return 0;
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}
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static void ds1307_clks_register(struct ds1307 *ds1307)
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{
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int ret;
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if (ds1307->type != ds_3231)
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return;
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ret = ds3231_clks_register(ds1307);
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if (ret) {
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dev_warn(&ds1307->client->dev,
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"unable to register clock device %d\n", ret);
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}
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}
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#else
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static void ds1307_clks_register(struct ds1307 *ds1307)
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{
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}
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#endif /* CONFIG_COMMON_CLK */
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static int ds1307_probe(struct i2c_client *client,
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const struct i2c_device_id *id)
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@ -1294,6 +1587,7 @@ read_rtc:
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}
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ds1307_hwmon_register(ds1307);
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ds1307_clks_register(ds1307);
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return 0;
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