clk: samsung: exynos5433: Add clocks for CMU_ATLAS domain
This patch adds the mux/divider/gate clocks for CMU_ATLAS domain which generates the clocks for Cortex-A57 Quad-core processsor, L2 cache controller and CoreSight. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Chanwoo Choi
Sylwester Nawrocki
parent
df40a13ca5
commit
6c5d76d15a
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@ -34,6 +34,9 @@ Required Properties:
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which generates clocks for GSCALER IPs.
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- "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO
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which generates clocks for Cortex-A53 Quad-core processor.
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- "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS
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which generates clocks for Cortex-A57 Quad-core processor, CoreSight and
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L2 cache controller.
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- reg: physical base address of the controller and length of memory mapped
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region.
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@ -111,6 +114,10 @@ Required Properties:
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- oscclk
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- sclk_bus_pll_apollo
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Input clocks for atlas clock controller:
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- oscclk
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- sclk_bus_pll_atlas
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume.
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@ -304,6 +311,15 @@ Example 2: Examples of clock controller nodes are listed below.
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clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
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};
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cmu_atlas: clock-controller@11800000 {
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compatible = "samsung,exynos5433-cmu-atlas";
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reg = <0x11800000 0x1088>;
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#clock-cells = <1>;
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clock-names = "oscclk", "sclk_bus_pll_atlas";
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clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
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};
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Example 3: UART controller node that consumes the clock generated by the clock
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controller.
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@ -3586,3 +3586,222 @@ static void __init exynos5433_cmu_apollo_init(struct device_node *np)
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}
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CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
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exynos5433_cmu_apollo_init);
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/*
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* Register offset definitions for CMU_ATLAS
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*/
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#define ATLAS_PLL_LOCK 0x0000
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#define ATLAS_PLL_CON0 0x0100
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#define ATLAS_PLL_CON1 0x0104
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#define ATLAS_PLL_FREQ_DET 0x010c
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#define MUX_SEL_ATLAS0 0x0200
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#define MUX_SEL_ATLAS1 0x0204
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#define MUX_SEL_ATLAS2 0x0208
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#define MUX_ENABLE_ATLAS0 0x0300
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#define MUX_ENABLE_ATLAS1 0x0304
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#define MUX_ENABLE_ATLAS2 0x0308
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#define MUX_STAT_ATLAS0 0x0400
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#define MUX_STAT_ATLAS1 0x0404
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#define MUX_STAT_ATLAS2 0x0408
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#define DIV_ATLAS0 0x0600
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#define DIV_ATLAS1 0x0604
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#define DIV_ATLAS_PLL_FREQ_DET 0x0608
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#define DIV_STAT_ATLAS0 0x0700
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#define DIV_STAT_ATLAS1 0x0704
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#define DIV_STAT_ATLAS_PLL_FREQ_DET 0x0708
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#define ENABLE_ACLK_ATLAS 0x0800
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#define ENABLE_PCLK_ATLAS 0x0900
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#define ENABLE_SCLK_ATLAS 0x0a00
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#define ENABLE_IP_ATLAS0 0x0b00
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#define ENABLE_IP_ATLAS1 0x0b04
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#define CLKOUT_CMU_ATLAS 0x0c00
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#define CLKOUT_CMU_ATLAS_DIV_STAT 0x0c04
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#define ARMCLK_STOPCTRL 0x1000
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#define ATLAS_PWR_CTRL 0x1020
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#define ATLAS_PWR_CTRL2 0x1024
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#define ATLAS_INTR_SPREAD_ENABLE 0x1080
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#define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084
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#define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088
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static unsigned long atlas_clk_regs[] __initdata = {
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ATLAS_PLL_LOCK,
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ATLAS_PLL_CON0,
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ATLAS_PLL_CON1,
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ATLAS_PLL_FREQ_DET,
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MUX_SEL_ATLAS0,
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MUX_SEL_ATLAS1,
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MUX_SEL_ATLAS2,
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MUX_ENABLE_ATLAS0,
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MUX_ENABLE_ATLAS1,
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MUX_ENABLE_ATLAS2,
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MUX_STAT_ATLAS0,
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MUX_STAT_ATLAS1,
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MUX_STAT_ATLAS2,
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DIV_ATLAS0,
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DIV_ATLAS1,
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DIV_ATLAS_PLL_FREQ_DET,
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DIV_STAT_ATLAS0,
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DIV_STAT_ATLAS1,
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DIV_STAT_ATLAS_PLL_FREQ_DET,
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ENABLE_ACLK_ATLAS,
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ENABLE_PCLK_ATLAS,
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ENABLE_SCLK_ATLAS,
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ENABLE_IP_ATLAS0,
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ENABLE_IP_ATLAS1,
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CLKOUT_CMU_ATLAS,
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CLKOUT_CMU_ATLAS_DIV_STAT,
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ARMCLK_STOPCTRL,
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ATLAS_PWR_CTRL,
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ATLAS_PWR_CTRL2,
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ATLAS_INTR_SPREAD_ENABLE,
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ATLAS_INTR_SPREAD_USE_STANDBYWFI,
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ATLAS_INTR_SPREAD_BLOCKING_DURATION,
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};
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/* list of all parent clock list */
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PNAME(mout_atlas_pll_p) = { "oscclk", "fout_atlas_pll", };
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PNAME(mout_bus_pll_atlas_user_p) = { "oscclk", "sclk_bus_pll_atlas", };
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PNAME(mout_atlas_p) = { "mout_atlas_pll",
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"mout_bus_pll_atlas_user", };
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static struct samsung_pll_clock atlas_pll_clks[] __initdata = {
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PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk",
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ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5443_pll_rates),
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};
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static struct samsung_mux_clock atlas_mux_clks[] __initdata = {
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/* MUX_SEL_ATLAS0 */
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MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p,
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MUX_SEL_ATLAS0, 0, 1, 0, CLK_MUX_READ_ONLY),
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/* MUX_SEL_ATLAS1 */
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MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user",
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mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1),
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/* MUX_SEL_ATLAS2 */
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MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2,
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0, 1, 0, CLK_MUX_READ_ONLY),
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};
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static struct samsung_div_clock atlas_div_clks[] __initdata = {
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/* DIV_ATLAS0 */
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DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2",
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DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE,
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CLK_DIVIDER_READ_ONLY),
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DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas",
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DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE,
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CLK_DIVIDER_READ_ONLY),
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DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2",
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DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE,
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CLK_DIVIDER_READ_ONLY),
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DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2",
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DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE,
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CLK_DIVIDER_READ_ONLY),
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DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2",
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DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE,
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CLK_DIVIDER_READ_ONLY),
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DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1",
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DIV_ATLAS0, 4, 3, CLK_GET_RATE_NOCACHE,
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CLK_DIVIDER_READ_ONLY),
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DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas",
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DIV_ATLAS0, 0, 3, CLK_GET_RATE_NOCACHE,
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CLK_DIVIDER_READ_ONLY),
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/* DIV_ATLAS1 */
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DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas",
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DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE,
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CLK_DIVIDER_READ_ONLY),
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DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas",
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DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE,
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CLK_DIVIDER_READ_ONLY),
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};
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static struct samsung_gate_clock atlas_gate_clks[] __initdata = {
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/* ENABLE_ACLK_ATLAS */
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GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys",
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"div_atclk_atlas", ENABLE_ACLK_ATLAS,
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9, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys",
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"div_atclk_atlas", ENABLE_ACLK_ATLAS,
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8, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys",
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"div_atclk_atlas", ENABLE_ACLK_ATLAS,
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7, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys",
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"div_atclk_atlas", ENABLE_ACLK_ATLAS,
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6, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys",
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"div_atclk_atlas", ENABLE_ACLK_ATLAS,
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5, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss",
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"div_atclk_atlas", ENABLE_ACLK_ATLAS,
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4, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix",
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"div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS,
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3, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci",
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"div_aclk_atlas", ENABLE_ACLK_ATLAS,
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2, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas",
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ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas",
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ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
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/* ENABLE_PCLK_ATLAS */
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GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys",
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"div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
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5, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys",
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"div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
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4, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys",
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"div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
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3, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas",
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ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas",
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ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas",
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ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
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/* ENABLE_SCLK_ATLAS */
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GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas",
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ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas",
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ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas",
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ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas",
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ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas",
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ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas",
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ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas",
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ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ATCLK, "atclk", "div_atclk_atlas",
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ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_SCLK_ATLAS, "sclk_atlas", "div_atlas2",
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ENABLE_SCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
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};
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static struct samsung_cmu_info atlas_cmu_info __initdata = {
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.pll_clks = atlas_pll_clks,
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.nr_pll_clks = ARRAY_SIZE(atlas_pll_clks),
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.mux_clks = atlas_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(atlas_mux_clks),
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.div_clks = atlas_div_clks,
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.nr_div_clks = ARRAY_SIZE(atlas_div_clks),
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.gate_clks = atlas_gate_clks,
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.nr_gate_clks = ARRAY_SIZE(atlas_gate_clks),
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.nr_clk_ids = ATLAS_NR_CLK,
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.clk_regs = atlas_clk_regs,
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.nr_clk_regs = ARRAY_SIZE(atlas_clk_regs),
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};
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static void __init exynos5433_cmu_atlas_init(struct device_node *np)
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{
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samsung_cmu_register_one(np, &atlas_cmu_info);
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}
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CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
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exynos5433_cmu_atlas_init);
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@ -891,4 +891,50 @@
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#define APOLLO_NR_CLK 31
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/* CMU_ATLAS */
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#define CLK_FOUT_ATLAS_PLL 1
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#define CLK_MOUT_ATLAS_PLL 2
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#define CLK_MOUT_BUS_PLL_ATLAS_USER 3
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#define CLK_MOUT_ATLAS 4
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#define CLK_DIV_CNTCLK_ATLAS 5
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#define CLK_DIV_PCLK_DBG_ATLAS 6
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#define CLK_DIV_ATCLK_ATLASO 7
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#define CLK_DIV_PCLK_ATLAS 8
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#define CLK_DIV_ACLK_ATLAS 9
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#define CLK_DIV_ATLAS2 10
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#define CLK_DIV_ATLAS1 11
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#define CLK_DIV_SCLK_HPM_ATLAS 12
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#define CLK_DIV_ATLAS_PLL 13
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#define CLK_ACLK_ATB_AUD_CSSYS 14
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#define CLK_ACLK_ATB_APOLLO3_CSSYS 15
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#define CLK_ACLK_ATB_APOLLO2_CSSYS 16
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#define CLK_ACLK_ATB_APOLLO1_CSSYS 17
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#define CLK_ACLK_ATB_APOLLO0_CSSYS 18
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#define CLK_ACLK_ASYNCAHBS_CSSYS_SSS 19
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#define CLK_ACLK_ASYNCAXIS_CSSYS_CCIX 20
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#define CLK_ACLK_ASYNCACES_ATLAS_CCI 21
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#define CLK_ACLK_AHB2APB_ATLASP 22
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#define CLK_ACLK_ATLASNP_200 23
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#define CLK_PCLK_ASYNCAPB_AUD_CSSYS 24
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#define CLK_PCLK_ASYNCAPB_ISP_CSSYS 25
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#define CLK_PCLK_ASYNCAPB_APOLLO_CSSYS 26
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#define CLK_PCLK_PMU_ATLAS 27
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#define CLK_PCLK_SYSREG_ATLAS 28
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#define CLK_PCLK_SECJTAG 29
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#define CLK_CNTCLK_ATLAS 30
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#define CLK_SCLK_FREQ_DET_ATLAS_PLL 31
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#define CLK_SCLK_HPM_ATLAS 32
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#define CLK_TRACECLK 33
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#define CLK_CTMCLK 34
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#define CLK_HCLK_CSSYS 35
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#define CLK_PCLK_DBG_CSSYS 36
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#define CLK_PCLK_DBG 37
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#define CLK_ATCLK 38
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#define CLK_SCLK_ATLAS 39
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#define ATLAS_NR_CLK 40
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
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