KVM/arm updates for 5.2-rc2
- Correctly annotate HYP-callable code to be non-traceable - Remove Christoffer from the MAINTAINERS file as his request -----BEGIN PGP SIGNATURE----- iQJJBAABCgAzFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAlzn+B4VHG1hcmMuenlu Z2llckBhcm0uY29tAAoJECPQ0LrRPXpD4aQQALuikHA7JTN2LUedPM8Klf7Hm0qO cqCdI1VmMxMJfzV2l/73JIJaB7wRPYugfsoGtrJMgpvs6nD8YMq8bpvDjwDIA2Wy SGMR0dNL+bhe+tWsYU9pR/9pBI9t7gSkWZY1Qv7SU4yNFOy1MV0dGtkCW5J6qhLh xoAUOmWdAj/KkaTRh4J9PtQeToiAtgFTlrnx/qC4iZGYT/gDOaXfPZTHerPeAEt6 MMKU74YoV5mX6Y55qw+dspDpSrxH44IkO0IF0ml/DvoQ+PaWjn6PFsx/3ZItdRg4 iiZefBm1dsvDGTIq1hzoEPJWahVmPad9cgsKSKhJPjHH79pWEsvRcExBmbku0Llj n1mmqMaKw64FLE5x/Vbbd8vHUoIdCpdBz+qWmeldHsXYHGge+c5HsoLbgHJqOFQD RidO+S+C9imaNYHnbehrAudjvav2bY/wbQCb+SKU2ZOXiuxXmdzlMNgiA61ylicK jqOvuNWISjhmVMJVK3GpkIs6pRwYeFwalNux809LqJTT9U9XnZARys/IdE16KlX/ 5FMM60r+B1aX6ge+w8MfyPw28xm8xwYnX4Mor7UfmDLCPB70w7MKCAIsHF12pCUf ygSnruajTgVic/2ARzum1FmY0boSdFcBRESN+eQpLriaJK3x7mHxS3qBrvd5Yj9j w1xfuKSCN+zGbHzq =v3an -----END PGP SIGNATURE----- Merge tag 'kvmarm-fixes-for-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD KVM/arm updates for 5.2-rc2 - Correctly annotate HYP-callable code to be non-traceable - Remove Christoffer from the MAINTAINERS file as his request
This commit is contained in:
Paolo Bonzini
commit
6bff2a3dc9
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@ -8611,14 +8611,12 @@ F: arch/x86/include/asm/svm.h
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F: arch/x86/kvm/svm.c
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KERNEL VIRTUAL MACHINE FOR ARM/ARM64 (KVM/arm, KVM/arm64)
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M: Christoffer Dall <christoffer.dall@arm.com>
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M: Marc Zyngier <marc.zyngier@arm.com>
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R: James Morse <james.morse@arm.com>
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R: Julien Thierry <julien.thierry@arm.com>
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R: Suzuki K Pouloze <suzuki.poulose@arm.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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L: kvmarm@lists.cs.columbia.edu
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W: http://systems.cs.columbia.edu/projects/kvm-arm
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git
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S: Maintained
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F: arch/arm/include/uapi/asm/kvm*
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@ -11,6 +11,7 @@ CFLAGS_ARMV7VE :=$(call cc-option, -march=armv7ve)
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obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/vgic-v3-sr.o
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obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/timer-sr.o
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obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/aarch32.o
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obj-$(CONFIG_KVM_ARM_HOST) += tlb.o
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obj-$(CONFIG_KVM_ARM_HOST) += cp15-sr.o
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@ -592,9 +592,6 @@ static inline int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu)
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void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr);
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void kvm_clr_pmu_events(u32 clr);
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void __pmu_switch_to_host(struct kvm_cpu_context *host_ctxt);
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bool __pmu_switch_to_guest(struct kvm_cpu_context *host_ctxt);
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void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu);
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void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu);
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#else
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@ -10,6 +10,7 @@ KVM=../../../../virt/kvm
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obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/vgic-v3-sr.o
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obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/timer-sr.o
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obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/aarch32.o
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obj-$(CONFIG_KVM_ARM_HOST) += vgic-v2-cpuif-proxy.o
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obj-$(CONFIG_KVM_ARM_HOST) += sysreg-sr.o
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@ -16,6 +16,7 @@
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*/
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#include <linux/arm-smccc.h>
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#include <linux/kvm_host.h>
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#include <linux/types.h>
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#include <linux/jump_label.h>
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#include <uapi/linux/psci.h>
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@ -505,6 +506,44 @@ static void __hyp_text __set_host_arch_workaround_state(struct kvm_vcpu *vcpu)
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#endif
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}
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/**
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* Disable host events, enable guest events
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*/
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static bool __hyp_text __pmu_switch_to_guest(struct kvm_cpu_context *host_ctxt)
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{
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struct kvm_host_data *host;
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struct kvm_pmu_events *pmu;
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host = container_of(host_ctxt, struct kvm_host_data, host_ctxt);
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pmu = &host->pmu_events;
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if (pmu->events_host)
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write_sysreg(pmu->events_host, pmcntenclr_el0);
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if (pmu->events_guest)
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write_sysreg(pmu->events_guest, pmcntenset_el0);
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return (pmu->events_host || pmu->events_guest);
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}
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/**
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* Disable guest events, enable host events
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*/
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static void __hyp_text __pmu_switch_to_host(struct kvm_cpu_context *host_ctxt)
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{
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struct kvm_host_data *host;
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struct kvm_pmu_events *pmu;
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host = container_of(host_ctxt, struct kvm_host_data, host_ctxt);
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pmu = &host->pmu_events;
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if (pmu->events_guest)
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write_sysreg(pmu->events_guest, pmcntenclr_el0);
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if (pmu->events_host)
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write_sysreg(pmu->events_host, pmcntenset_el0);
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}
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/* Switch to the guest for VHE systems running in EL2 */
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int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)
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{
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@ -53,44 +53,6 @@ void kvm_clr_pmu_events(u32 clr)
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ctx->pmu_events.events_guest &= ~clr;
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}
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/**
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* Disable host events, enable guest events
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*/
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bool __hyp_text __pmu_switch_to_guest(struct kvm_cpu_context *host_ctxt)
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{
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struct kvm_host_data *host;
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struct kvm_pmu_events *pmu;
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host = container_of(host_ctxt, struct kvm_host_data, host_ctxt);
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pmu = &host->pmu_events;
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if (pmu->events_host)
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write_sysreg(pmu->events_host, pmcntenclr_el0);
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if (pmu->events_guest)
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write_sysreg(pmu->events_guest, pmcntenset_el0);
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return (pmu->events_host || pmu->events_guest);
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}
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/**
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* Disable guest events, enable host events
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*/
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void __hyp_text __pmu_switch_to_host(struct kvm_cpu_context *host_ctxt)
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{
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struct kvm_host_data *host;
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struct kvm_pmu_events *pmu;
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host = container_of(host_ctxt, struct kvm_host_data, host_ctxt);
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pmu = &host->pmu_events;
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if (pmu->events_guest)
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write_sysreg(pmu->events_guest, pmcntenclr_el0);
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if (pmu->events_host)
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write_sysreg(pmu->events_host, pmcntenset_el0);
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}
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#define PMEVTYPER_READ_CASE(idx) \
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case idx: \
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return read_sysreg(pmevtyper##idx##_el0)
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@ -25,127 +25,6 @@
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_hyp.h>
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/*
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* stolen from arch/arm/kernel/opcodes.c
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*
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* condition code lookup table
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* index into the table is test code: EQ, NE, ... LT, GT, AL, NV
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*
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* bit position in short is condition code: NZCV
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*/
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static const unsigned short cc_map[16] = {
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0xF0F0, /* EQ == Z set */
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0x0F0F, /* NE */
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0xCCCC, /* CS == C set */
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0x3333, /* CC */
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0xFF00, /* MI == N set */
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0x00FF, /* PL */
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0xAAAA, /* VS == V set */
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0x5555, /* VC */
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0x0C0C, /* HI == C set && Z clear */
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0xF3F3, /* LS == C clear || Z set */
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0xAA55, /* GE == (N==V) */
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0x55AA, /* LT == (N!=V) */
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0x0A05, /* GT == (!Z && (N==V)) */
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0xF5FA, /* LE == (Z || (N!=V)) */
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0xFFFF, /* AL always */
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0 /* NV */
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};
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/*
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* Check if a trapped instruction should have been executed or not.
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*/
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bool __hyp_text kvm_condition_valid32(const struct kvm_vcpu *vcpu)
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{
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unsigned long cpsr;
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u32 cpsr_cond;
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int cond;
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/* Top two bits non-zero? Unconditional. */
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if (kvm_vcpu_get_hsr(vcpu) >> 30)
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return true;
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/* Is condition field valid? */
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cond = kvm_vcpu_get_condition(vcpu);
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if (cond == 0xE)
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return true;
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cpsr = *vcpu_cpsr(vcpu);
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if (cond < 0) {
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/* This can happen in Thumb mode: examine IT state. */
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unsigned long it;
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it = ((cpsr >> 8) & 0xFC) | ((cpsr >> 25) & 0x3);
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/* it == 0 => unconditional. */
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if (it == 0)
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return true;
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/* The cond for this insn works out as the top 4 bits. */
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cond = (it >> 4);
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}
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cpsr_cond = cpsr >> 28;
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if (!((cc_map[cond] >> cpsr_cond) & 1))
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return false;
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return true;
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}
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/**
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* adjust_itstate - adjust ITSTATE when emulating instructions in IT-block
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* @vcpu: The VCPU pointer
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*
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* When exceptions occur while instructions are executed in Thumb IF-THEN
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* blocks, the ITSTATE field of the CPSR is not advanced (updated), so we have
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* to do this little bit of work manually. The fields map like this:
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*
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* IT[7:0] -> CPSR[26:25],CPSR[15:10]
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*/
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static void __hyp_text kvm_adjust_itstate(struct kvm_vcpu *vcpu)
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{
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unsigned long itbits, cond;
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unsigned long cpsr = *vcpu_cpsr(vcpu);
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bool is_arm = !(cpsr & PSR_AA32_T_BIT);
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if (is_arm || !(cpsr & PSR_AA32_IT_MASK))
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return;
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cond = (cpsr & 0xe000) >> 13;
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itbits = (cpsr & 0x1c00) >> (10 - 2);
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itbits |= (cpsr & (0x3 << 25)) >> 25;
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/* Perform ITAdvance (see page A2-52 in ARM DDI 0406C) */
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if ((itbits & 0x7) == 0)
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itbits = cond = 0;
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else
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itbits = (itbits << 1) & 0x1f;
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cpsr &= ~PSR_AA32_IT_MASK;
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cpsr |= cond << 13;
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cpsr |= (itbits & 0x1c) << (10 - 2);
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cpsr |= (itbits & 0x3) << 25;
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*vcpu_cpsr(vcpu) = cpsr;
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}
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/**
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* kvm_skip_instr - skip a trapped instruction and proceed to the next
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* @vcpu: The vcpu pointer
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*/
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void __hyp_text kvm_skip_instr32(struct kvm_vcpu *vcpu, bool is_wide_instr)
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{
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bool is_thumb;
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is_thumb = !!(*vcpu_cpsr(vcpu) & PSR_AA32_T_BIT);
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if (is_thumb && !is_wide_instr)
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*vcpu_pc(vcpu) += 2;
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else
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*vcpu_pc(vcpu) += 4;
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kvm_adjust_itstate(vcpu);
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}
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/*
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* Table taken from ARMv8 ARM DDI0487B-B, table G1-10.
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*/
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@ -0,0 +1,136 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Hyp portion of the (not much of an) Emulation layer for 32bit guests.
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*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* based on arch/arm/kvm/emulate.c
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*/
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#include <linux/kvm_host.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_hyp.h>
|
||||
|
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/*
|
||||
* stolen from arch/arm/kernel/opcodes.c
|
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*
|
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* condition code lookup table
|
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* index into the table is test code: EQ, NE, ... LT, GT, AL, NV
|
||||
*
|
||||
* bit position in short is condition code: NZCV
|
||||
*/
|
||||
static const unsigned short cc_map[16] = {
|
||||
0xF0F0, /* EQ == Z set */
|
||||
0x0F0F, /* NE */
|
||||
0xCCCC, /* CS == C set */
|
||||
0x3333, /* CC */
|
||||
0xFF00, /* MI == N set */
|
||||
0x00FF, /* PL */
|
||||
0xAAAA, /* VS == V set */
|
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0x5555, /* VC */
|
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0x0C0C, /* HI == C set && Z clear */
|
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0xF3F3, /* LS == C clear || Z set */
|
||||
0xAA55, /* GE == (N==V) */
|
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0x55AA, /* LT == (N!=V) */
|
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0x0A05, /* GT == (!Z && (N==V)) */
|
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0xF5FA, /* LE == (Z || (N!=V)) */
|
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0xFFFF, /* AL always */
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0 /* NV */
|
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};
|
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|
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/*
|
||||
* Check if a trapped instruction should have been executed or not.
|
||||
*/
|
||||
bool __hyp_text kvm_condition_valid32(const struct kvm_vcpu *vcpu)
|
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{
|
||||
unsigned long cpsr;
|
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u32 cpsr_cond;
|
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int cond;
|
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|
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/* Top two bits non-zero? Unconditional. */
|
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if (kvm_vcpu_get_hsr(vcpu) >> 30)
|
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return true;
|
||||
|
||||
/* Is condition field valid? */
|
||||
cond = kvm_vcpu_get_condition(vcpu);
|
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if (cond == 0xE)
|
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return true;
|
||||
|
||||
cpsr = *vcpu_cpsr(vcpu);
|
||||
|
||||
if (cond < 0) {
|
||||
/* This can happen in Thumb mode: examine IT state. */
|
||||
unsigned long it;
|
||||
|
||||
it = ((cpsr >> 8) & 0xFC) | ((cpsr >> 25) & 0x3);
|
||||
|
||||
/* it == 0 => unconditional. */
|
||||
if (it == 0)
|
||||
return true;
|
||||
|
||||
/* The cond for this insn works out as the top 4 bits. */
|
||||
cond = (it >> 4);
|
||||
}
|
||||
|
||||
cpsr_cond = cpsr >> 28;
|
||||
|
||||
if (!((cc_map[cond] >> cpsr_cond) & 1))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* adjust_itstate - adjust ITSTATE when emulating instructions in IT-block
|
||||
* @vcpu: The VCPU pointer
|
||||
*
|
||||
* When exceptions occur while instructions are executed in Thumb IF-THEN
|
||||
* blocks, the ITSTATE field of the CPSR is not advanced (updated), so we have
|
||||
* to do this little bit of work manually. The fields map like this:
|
||||
*
|
||||
* IT[7:0] -> CPSR[26:25],CPSR[15:10]
|
||||
*/
|
||||
static void __hyp_text kvm_adjust_itstate(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
unsigned long itbits, cond;
|
||||
unsigned long cpsr = *vcpu_cpsr(vcpu);
|
||||
bool is_arm = !(cpsr & PSR_AA32_T_BIT);
|
||||
|
||||
if (is_arm || !(cpsr & PSR_AA32_IT_MASK))
|
||||
return;
|
||||
|
||||
cond = (cpsr & 0xe000) >> 13;
|
||||
itbits = (cpsr & 0x1c00) >> (10 - 2);
|
||||
itbits |= (cpsr & (0x3 << 25)) >> 25;
|
||||
|
||||
/* Perform ITAdvance (see page A2-52 in ARM DDI 0406C) */
|
||||
if ((itbits & 0x7) == 0)
|
||||
itbits = cond = 0;
|
||||
else
|
||||
itbits = (itbits << 1) & 0x1f;
|
||||
|
||||
cpsr &= ~PSR_AA32_IT_MASK;
|
||||
cpsr |= cond << 13;
|
||||
cpsr |= (itbits & 0x1c) << (10 - 2);
|
||||
cpsr |= (itbits & 0x3) << 25;
|
||||
*vcpu_cpsr(vcpu) = cpsr;
|
||||
}
|
||||
|
||||
/**
|
||||
* kvm_skip_instr - skip a trapped instruction and proceed to the next
|
||||
* @vcpu: The vcpu pointer
|
||||
*/
|
||||
void __hyp_text kvm_skip_instr32(struct kvm_vcpu *vcpu, bool is_wide_instr)
|
||||
{
|
||||
bool is_thumb;
|
||||
|
||||
is_thumb = !!(*vcpu_cpsr(vcpu) & PSR_AA32_T_BIT);
|
||||
if (is_thumb && !is_wide_instr)
|
||||
*vcpu_pc(vcpu) += 2;
|
||||
else
|
||||
*vcpu_pc(vcpu) += 4;
|
||||
kvm_adjust_itstate(vcpu);
|
||||
}
|
||||
Loading…
Reference in New Issue