From 6b342707a1ecb550f05a4441d6b2dc593a22e5b3 Mon Sep 17 00:00:00 2001 From: Qi Liu Date: Thu, 24 Feb 2022 19:11:29 +0800 Subject: [PATCH] perf jevents: Add support for HiSilicon CPA PMU aliasing Add support for HiSilicon CPA PMU aliasing. The kernel driver is in drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c Reviewed-by: John Garry Signed-off-by: Qi Liu Cc: Mark Rutland Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Cc: linuxarm@huawei.com Link: https://lore.kernel.org/r/20220224111129.41416-3-liuqi115@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arm64/hisilicon/hip09/sys/uncore-cpa.json | 81 +++++++++++++++++++ tools/perf/pmu-events/jevents.c | 1 + 2 files changed, 82 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json new file mode 100644 index 000000000000..7bcddec8a84f --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json @@ -0,0 +1,81 @@ +[ + { + "ConfigCode": "0x00", + "EventName": "cpa_cycles", + "BriefDescription": "count of CPA cycles", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "ConfigCode": "0x61", + "EventName": "cpa_p1_wr_dat", + "BriefDescription": "Number of write ops transmitted by the P1 port", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "ConfigCode": "0x62", + "EventName": "cpa_p1_rd_dat", + "BriefDescription": "Number of read ops transmitted by the P1 port", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "ConfigCode": "0x3", + "EventName": "cpa_p1_rd_dat_64b", + "BriefDescription": "Number of read ops transmitted by the P1 port which size is 64 bytes", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "ConfigCode": "0x4", + "EventName": "cpa_p1_rd_dat_32b", + "BriefDescription": "Number of read ops transmitted by the P1 port which size is 32 bytes", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "ConfigCode": "0xE1", + "EventName": "cpa_p0_wr_dat", + "BriefDescription": "Number of write ops transmitted by the P0 port", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "ConfigCode": "0xE2", + "EventName": "cpa_p0_rd_dat", + "BriefDescription": "Number of read ops transmitted by the P0 port", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "ConfigCode": "0x83", + "EventName": "cpa_p0_rd_dat_64b", + "BriefDescription": "Number of read ops transmitted by the P0 port which size is 64 bytes", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "ConfigCode": "0x84", + "EventName": "cpa_p0_rd_dat_32b", + "BriefDescription": "Number of read ops transmitted by the P0 port which size is 32 bytes", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "MetricExpr": "(cpa_p1_wr_dat * 64 + cpa_p1_rd_dat_64b * 64 + cpa_p1_rd_dat_32b * 32) / cpa_cycles", + "BriefDescription": "Average bandwidth of CPA Port 1", + "MetricGroup": "CPA", + "MetricName": "cpa_p1_avg_bw", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "MetricExpr": "(cpa_p0_wr_dat * 64 + cpa_p0_rd_dat_64b * 64 + cpa_p0_rd_dat_32b * 32) / cpa_cycles", + "BriefDescription": "Average bandwidth of CPA Port 0", + "MetricGroup": "CPA", + "MetricName": "cpa_p0_avg_bw", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + } +] diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c index 1a57c3f81dd4..159d9eab6e79 100644 --- a/tools/perf/pmu-events/jevents.c +++ b/tools/perf/pmu-events/jevents.c @@ -277,6 +277,7 @@ static struct map { { "CPU-M-CF", "cpum_cf" }, { "CPU-M-SF", "cpum_sf" }, { "UPI LL", "uncore_upi" }, + { "hisi_sicl,cpa", "hisi_sicl,cpa"}, { "hisi_sccl,ddrc", "hisi_sccl,ddrc" }, { "hisi_sccl,hha", "hisi_sccl,hha" }, { "hisi_sccl,l3c", "hisi_sccl,l3c" },