perf jevents: Add support for HiSilicon CPA PMU aliasing
Add support for HiSilicon CPA PMU aliasing. The kernel driver is in drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Qi Liu <liuqi115@huawei.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linuxarm@huawei.com Link: https://lore.kernel.org/r/20220224111129.41416-3-liuqi115@huawei.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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@ -0,0 +1,81 @@
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[
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{
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"ConfigCode": "0x00",
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"EventName": "cpa_cycles",
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"BriefDescription": "count of CPA cycles",
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"Compat": "0x00000030",
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"Unit": "hisi_sicl,cpa"
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},
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{
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"ConfigCode": "0x61",
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"EventName": "cpa_p1_wr_dat",
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"BriefDescription": "Number of write ops transmitted by the P1 port",
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"Compat": "0x00000030",
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"Unit": "hisi_sicl,cpa"
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},
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{
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"ConfigCode": "0x62",
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"EventName": "cpa_p1_rd_dat",
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"BriefDescription": "Number of read ops transmitted by the P1 port",
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"Compat": "0x00000030",
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"Unit": "hisi_sicl,cpa"
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},
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{
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"ConfigCode": "0x3",
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"EventName": "cpa_p1_rd_dat_64b",
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"BriefDescription": "Number of read ops transmitted by the P1 port which size is 64 bytes",
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"Compat": "0x00000030",
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"Unit": "hisi_sicl,cpa"
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},
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{
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"ConfigCode": "0x4",
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"EventName": "cpa_p1_rd_dat_32b",
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"BriefDescription": "Number of read ops transmitted by the P1 port which size is 32 bytes",
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"Compat": "0x00000030",
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"Unit": "hisi_sicl,cpa"
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},
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{
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"ConfigCode": "0xE1",
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"EventName": "cpa_p0_wr_dat",
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"BriefDescription": "Number of write ops transmitted by the P0 port",
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"Compat": "0x00000030",
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"Unit": "hisi_sicl,cpa"
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},
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{
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"ConfigCode": "0xE2",
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"EventName": "cpa_p0_rd_dat",
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"BriefDescription": "Number of read ops transmitted by the P0 port",
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"Compat": "0x00000030",
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"Unit": "hisi_sicl,cpa"
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},
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{
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"ConfigCode": "0x83",
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"EventName": "cpa_p0_rd_dat_64b",
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"BriefDescription": "Number of read ops transmitted by the P0 port which size is 64 bytes",
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"Compat": "0x00000030",
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"Unit": "hisi_sicl,cpa"
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},
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{
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"ConfigCode": "0x84",
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"EventName": "cpa_p0_rd_dat_32b",
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"BriefDescription": "Number of read ops transmitted by the P0 port which size is 32 bytes",
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"Compat": "0x00000030",
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"Unit": "hisi_sicl,cpa"
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},
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{
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"MetricExpr": "(cpa_p1_wr_dat * 64 + cpa_p1_rd_dat_64b * 64 + cpa_p1_rd_dat_32b * 32) / cpa_cycles",
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"BriefDescription": "Average bandwidth of CPA Port 1",
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"MetricGroup": "CPA",
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"MetricName": "cpa_p1_avg_bw",
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"Compat": "0x00000030",
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"Unit": "hisi_sicl,cpa"
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},
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{
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"MetricExpr": "(cpa_p0_wr_dat * 64 + cpa_p0_rd_dat_64b * 64 + cpa_p0_rd_dat_32b * 32) / cpa_cycles",
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"BriefDescription": "Average bandwidth of CPA Port 0",
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"MetricGroup": "CPA",
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"MetricName": "cpa_p0_avg_bw",
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"Compat": "0x00000030",
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"Unit": "hisi_sicl,cpa"
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}
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]
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@ -277,6 +277,7 @@ static struct map {
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{ "CPU-M-CF", "cpum_cf" },
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{ "CPU-M-SF", "cpum_sf" },
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{ "UPI LL", "uncore_upi" },
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{ "hisi_sicl,cpa", "hisi_sicl,cpa"},
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{ "hisi_sccl,ddrc", "hisi_sccl,ddrc" },
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{ "hisi_sccl,hha", "hisi_sccl,hha" },
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{ "hisi_sccl,l3c", "hisi_sccl,l3c" },
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