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[POWERPC] 85xxCDS: MPC8548 DTS cleanup. 

Added the P2P bridge present on the Arcadia base board and moved the VIA
Southbridge behind the bridge to reflect its actual position in the bus
organization. Added the RTC that's in the VIA Southbridge and expanded
the ranges array for the SOC node to allow proper address translation of
the RTC registers.

Signed-off-by: Randy Vinson <rvinson@mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Randy Vinson 2007-07-17 16:37:12 -07:00 committed by Kumar Gala
parent 8d7bc8f9d1
commit 6af0125742
1 changed files with 89 additions and 35 deletions
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124
arch/powerpc/boot/dts/mpc8548cds.dts
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@ -44,8 +44,14 @@
#size-cells = <1>; #size-cells = <1>;
#interrupt-cells = <2>; #interrupt-cells = <2>;
device_type = "soc"; device_type = "soc";
ranges = <0 e0000000 00100000>; ranges = <00001000 e0001000 000ff000
reg = <e0000000 00100000>; // CCSRBAR 1M 80000000 80000000 10000000
e2000000 e2000000 00800000
90000000 90000000 10000000
e2800000 e2800000 00800000
a0000000 a0000000 20000000
e3000000 e3000000 01000000>;
reg = <e0000000 00001000>; // CCSRBAR
bus-frequency = <0>; bus-frequency = <0>;
memory-controller@2000 { memory-controller@2000 {
@ -162,8 +168,8 @@
serial@4500 { serial@4500 {
device_type = "serial"; device_type = "serial";
compatible = "ns16550"; compatible = "ns16550";
reg = <4500 100>; // reg base, size reg = <4500 100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot? clock-frequency = <0>; // should we fill in in uboot?
interrupts = <2a 2>; interrupts = <2a 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
}; };
@ -172,7 +178,7 @@
device_type = "serial"; device_type = "serial";
compatible = "ns16550"; compatible = "ns16550";
reg = <4600 100>; // reg base, size reg = <4600 100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot? clock-frequency = <0>; // should we fill in in uboot?
interrupts = <2a 2>; interrupts = <2a 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
}; };
@ -183,8 +189,8 @@
fsl,has-rstcr; fsl,has-rstcr;
}; };
pci1: pci@8000 { pci@8000 {
interrupt-map-mask = <1f800 0 0 7>; interrupt-map-mask = <f800 0 0 7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x4 (PCIX Slot 2) */ /* IDSEL 0x4 (PCIX Slot 2) */
02000 0 0 1 &mpic 0 1 02000 0 0 1 &mpic 0 1
@ -244,19 +250,7 @@
0E000 0 0 1 &mpic 0 1 0E000 0 0 1 &mpic 0 1
0E000 0 0 2 &mpic 1 1 0E000 0 0 2 &mpic 1 1
0E000 0 0 3 &mpic 2 1 0E000 0 0 3 &mpic 2 1
0E000 0 0 4 &mpic 3 1 0E000 0 0 4 &mpic 3 1>;
/* bus 1 , idsel 0x2 Tsi310 bridge secondary */
11000 0 0 1 &mpic 2 1
11000 0 0 2 &mpic 3 1
11000 0 0 3 &mpic 0 1
11000 0 0 4 &mpic 1 1
/* VIA chip */
12000 0 0 1 &mpic 0 1
12000 0 0 2 &mpic 1 1
12000 0 0 3 &mpic 2 1
12000 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <18 2>; interrupts = <18 2>;
@ -271,18 +265,78 @@
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci"; device_type = "pci";
i8259@4 { pci_bridge@1c {
clock-frequency = <0>; interrupt-map-mask = <f800 0 0 7>;
interrupt-controller; interrupt-map = <
device_type = "interrupt-controller";
reg = <12000 0 0 0 1>; /* IDSEL 0x00 (PrPMC Site) */
#address-cells = <0>; 0000 0 0 1 &mpic 0 1
#interrupt-cells = <2>; 0000 0 0 2 &mpic 1 1
built-in; 0000 0 0 3 &mpic 2 1
compatible = "chrp,iic"; 0000 0 0 4 &mpic 3 1
big-endian;
interrupts = <1>; /* IDSEL 0x04 (VIA chip) */
interrupt-parent = <&pci1>; 2000 0 0 1 &mpic 0 1
2000 0 0 2 &mpic 1 1
2000 0 0 3 &mpic 2 1
2000 0 0 4 &mpic 3 1
/* IDSEL 0x05 (8139) */
2800 0 0 1 &mpic 1 1
/* IDSEL 0x06 (Slot 6) */
3000 0 0 1 &mpic 2 1
3000 0 0 2 &mpic 3 1
3000 0 0 3 &mpic 0 1
3000 0 0 4 &mpic 1 1
/* IDESL 0x07 (Slot 7) */
3800 0 0 1 &mpic 3 1
3800 0 0 2 &mpic 0 1
3800 0 0 3 &mpic 1 1
3800 0 0 4 &mpic 2 1>;
reg = <e000 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <02000000 0 80000000
02000000 0 80000000
0 20000000
01000000 0 00000000
01000000 0 00000000
0 00080000>;
clock-frequency = <1fca055>;
isa@4 {
device_type = "isa";
#interrupt-cells = <2>;
#size-cells = <1>;
#address-cells = <2>;
reg = <2000 0 0 0 0>;
ranges = <1 0 01000000 0 0 00001000>;
interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 {
clock-frequency = <0>;
interrupt-controller;
device_type = "interrupt-controller";
reg = <1 20 2
1 a0 2
1 4d0 2>;
#address-cells = <0>;
#interrupt-cells = <2>;
built-in;
compatible = "chrp,iic";
interrupts = <0 1>;
interrupt-parent = <&mpic>;
};
rtc@70 {
compatible = "pnpPNP,b00";
reg = <1 70 2>;
};
};
}; };
}; };
@ -292,9 +346,9 @@
/* IDSEL 0x15 */ /* IDSEL 0x15 */
a800 0 0 1 &mpic b 1 a800 0 0 1 &mpic b 1
a800 0 0 2 &mpic b 1 a800 0 0 2 &mpic 1 1
a800 0 0 3 &mpic b 1 a800 0 0 3 &mpic 2 1
a800 0 0 4 &mpic b 1>; a800 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <19 2>; interrupts = <19 2>;