iio: adc: meson: init channels 0,1 input muxes
Set up input channels 0,1 muxes in the same way as for the channels 2-7 later in the code. Signed-off-by: George Stark <gnstark@sberdevices.ru> Link: https://lore.kernel.org/r/20230715110654.6035-2-gnstark@sberdevices.ru Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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@ -899,6 +899,22 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev)
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MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK,
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regval);
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regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
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MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW,
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MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW);
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regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
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MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW,
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MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW);
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regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
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MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW,
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MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW);
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regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
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MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW,
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MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW);
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/*
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* set up the input channel muxes in MESON_SAR_ADC_AUX_SW
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* (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable
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