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ARM: dts: lan966x: add MIIM nodes 

Add the MDIO controller nodes. The integrated PHYs are connected to the
second controller. This controller also takes care of the resets of the
integrated PHYs, thus it has two memory regions. The first controller
is routed to the external MDIO/MDC pins.

By default, they are disabled.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220502224127.2604333-10-michael@walle.cc
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
This commit is contained in:
Michael Walle 2022-05-03 00:41:23 +02:00 committed by Claudiu Beznea
parent 63f295940d
commit 6ad69e07de
1 changed files with 31 additions and 0 deletions
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31
arch/arm/boot/dts/lan966x.dtsi
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@ -418,6 +418,37 @@
#interrupt-cells = <2>;
};
mdio0: mdio@e2004118 {
compatible = "microchip,lan966x-miim";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xe2004118 0x24>;
clocks = <&sys_clk>;
status = "disabled";
};
mdio1: mdio@e200413c {
compatible = "microchip,lan966x-miim";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xe200413c 0x24>,
<0xe2010020 0x4>;
clocks = <&sys_clk>;
status = "disabled";
phy0: ethernet-phy@1 {
reg = <1>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
phy1: ethernet-phy@2 {
reg = <2>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
sgpio: gpio@e2004190 {
compatible = "microchip,sparx5-sgpio";
reg = <0xe2004190 0x118>;