dt-bindings: watchdog: Add i.MX7ULP bindings
Add the watchdog bindings for Freescale i.MX7ULP. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Rob Herring <rohb@kernel.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/1566999303-18795-1-git-send-email-Anson.Huang@nxp.com Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
This commit is contained in:
parent
284ec100d0
commit
69eb8b1186
|
@ -0,0 +1,22 @@
|
|||
* Freescale i.MX7ULP Watchdog Timer (WDT) Controller
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "fsl,imx7ulp-wdt"
|
||||
- reg : Should contain WDT registers location and length
|
||||
- interrupts : Should contain WDT interrupt
|
||||
- clocks: Should contain a phandle pointing to the gated peripheral clock.
|
||||
|
||||
Optional properties:
|
||||
- timeout-sec : Contains the watchdog timeout in seconds
|
||||
|
||||
Examples:
|
||||
|
||||
wdog1: watchdog@403d0000 {
|
||||
compatible = "fsl,imx7ulp-wdt";
|
||||
reg = <0x403d0000 0x10000>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
|
||||
assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
|
||||
assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
|
||||
timeout-sec = <40>;
|
||||
};
|
Loading…
Reference in New Issue