clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks
On R-Car Gen3 SoCs with a Spread Spectrum Clock Generator (e.g. R-Car D3), a peripheral clock divider has been added, to select between clean and spread spectrum parents. Add a new clock type to the R-Car Gen3 driver core to handle this. To avoid increasing the size of struct cpg_core_clk, both parents and dividers are stored in the existing parent resp. div fields. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -272,7 +272,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
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unsigned int div = 1;
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u32 value;
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parent = clks[core->parent];
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parent = clks[core->parent & 0xffff]; /* CLK_TYPE_PE uses high bits */
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if (IS_ERR(parent))
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return ERR_CAST(parent);
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@ -355,6 +355,24 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
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parent = clks[cpg_clk_extalr];
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break;
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case CLK_TYPE_GEN3_PE:
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/*
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* Peripheral clock with a fixed divider, selectable between
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* clean and spread spectrum parents using MD12
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*/
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if (cpg_mode & BIT(12)) {
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/* Clean */
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div = core->div & 0xffff;
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} else {
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/* SCCG */
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parent = clks[core->parent >> 16];
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if (IS_ERR(parent))
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return ERR_CAST(parent);
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div = core->div >> 16;
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}
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mult = 1;
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break;
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default:
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return ERR_PTR(-EINVAL);
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}
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@ -20,11 +20,18 @@ enum rcar_gen3_clk_types {
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CLK_TYPE_GEN3_PLL4,
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CLK_TYPE_GEN3_SD,
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CLK_TYPE_GEN3_R,
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CLK_TYPE_GEN3_PE,
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};
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#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
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#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
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_div_clean) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE, \
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(_parent_sscg) << 16 | (_parent_clean), \
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.div = (_div_sscg) << 16 | (_div_clean))
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struct rcar_gen3_cpg_pll_config {
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u8 extal_div;
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u8 pll1_mult;
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