drm/amd/display: DCN2 Engine-specifc encoder allocation
[WHY] From DCE110 onward, we have the ability to assign DIG BE and FE separately for any display connector type; before, we could only do this for DP. Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2446,8 +2446,9 @@ static struct resource_funcs dcn20_res_pool_funcs = {
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.set_mcif_arb_params = dcn20_set_mcif_arb_params,
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.set_mcif_arb_params = dcn20_set_mcif_arb_params,
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#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
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#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
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.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
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.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
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.remove_dsc_from_stream_resource = dcn20_remove_dsc_from_stream_resource
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.remove_dsc_from_stream_resource = dcn20_remove_dsc_from_stream_resource,
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#endif
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#endif
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.find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link
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};
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};
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bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
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bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
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