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rtlwifi: correct comment 

Correct comment.  Set bit 3 and bit 4 of 0x0005 register (REG_APS_FSMCO + 1)
to 0 which means disable WL suspend, not enable WL suspend.

Signed-off-by: Kevin Lo <kevlo@kevlo.org>
Acked-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
This commit is contained in:
Kevin Lo 2018-03-17 22:26:07 +08:00 committed by Kalle Valo
parent c378894725
commit 692f5deccd
5 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
View File

@ -142,7 +142,7 @@
/*wait power state to suspend*/}, \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0 \
/*0x04[12:11] = 2b'01enable WL suspend*/},
/*0x04[12:11] = 2b'00 disable WL suspend*/},
#define RTL8188EE_TRANS_CARDEMU_TO_CARDDIS \
{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
@ -179,7 +179,7 @@
/*wait power state to suspend*/}, \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0 \
/*0x04[12:11] = 2b'01enable WL suspend*/},
/*0x04[12:11] = 2b'00 disable WL suspend*/},
#define RTL8188EE_TRANS_CARDEMU_TO_PDN \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \

4
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
View File

@ -134,7 +134,7 @@
/*wait power state to suspend*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), BIT(1)}, \
/*0x04[12:11] = 2b'01enable WL suspend*/ \
/*0x04[12:11] = 2b'00 disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
@ -181,7 +181,7 @@
/*Lock small LDO Register*/ \
{0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0}, \
/*0x04[12:11] = 2b'01enable WL suspend*/ \
/*0x04[12:11] = 2b'00 disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},

4
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
View File

@ -135,7 +135,7 @@
/*wait power state to suspend*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},\
/*0x04[12:11] = 2b'01enable WL suspend*/ \
/*0x04[12:11] = 2b'00 disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
@ -172,7 +172,7 @@
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
PWR_CMD_POLLING, BIT(1), BIT(1)},\
/*0x04[12:11] = 2b'00enable WL suspend*/ \
/*0x04[12:11] = 2b'00 disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
PWR_CMD_WRITE, BIT(3)|BIT(4), 0},\

4
drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h
View File

@ -204,7 +204,7 @@
/*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
/*0x04[12:11] = 2b'01enable WL suspend*/ \
/*0x04[12:11] = 2b'00 disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
@ -251,7 +251,7 @@
/*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
/*0x04[12:11] = 2b'01enable WL suspend*/ \
/*0x04[12:11] = 2b'00 disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, \
/*0x23[4] = 1b'0 12H LDO enter normal mode*/ \

4
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
View File

@ -531,7 +531,7 @@ extern struct wlan_pwr_cfg rtl8812_leave_lps_flow
/*0x23[4] = 1b'0 12H LDO enter normal mode*/}, \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
/*0x04[12:11] = 2b'01enable WL suspend*/},
/*0x04[12:11] = 2b'00 disable WL suspend*/},
#define RTL8821A_TRANS_CARDEMU_TO_CARDDIS \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
@ -572,7 +572,7 @@ extern struct wlan_pwr_cfg rtl8812_leave_lps_flow
/*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/}, \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
/*0x04[12:11] = 2b'01enable WL suspend*/},\
/*0x04[12:11] = 2b'00 disable WL suspend*/},\
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
/*0x23[4] = 1b'0 12H LDO enter normal mode*/}, \