drm/exynos/hdmi: add Exynos5433 support
HDMI on Exynos5433 differs from previous versions: - different HDMI-PHY settings, - different clocks, - SYSREG registers for enabling reference clock, - MODE_SET register in HDMI-PHY. It is distinguished from other variants by different compatible string. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
This commit is contained in:
Andrzej Hajda
Inki Dae
parent
2f1cad0d2d
commit
68cd004e54
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@ -112,6 +112,7 @@ struct string_array_spec {
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struct hdmi_driver_data {
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unsigned int type;
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unsigned int is_apb_phy:1;
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unsigned int has_sysreg:1;
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struct hdmiphy_configs phy_confs;
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struct string_array_spec clk_gates;
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/*
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@ -140,6 +141,7 @@ struct hdmi_context {
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struct gpio_desc *hpd_gpio;
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int irq;
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struct regmap *pmureg;
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struct regmap *sysreg;
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struct clk **clk_gates;
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struct clk **clk_muxes;
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struct regulator_bulk_data regul_bulk[ARRAY_SIZE(supply)];
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@ -516,6 +518,90 @@ static const struct hdmiphy_config hdmiphy_5420_configs[] = {
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},
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};
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static const struct hdmiphy_config hdmiphy_5433_configs[] = {
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{
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.pixel_clock = 27000000,
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.conf = {
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0x01, 0x51, 0x22, 0x51, 0x08, 0xfc, 0x88, 0x46,
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0x72, 0x50, 0x24, 0x0c, 0x24, 0x0f, 0x7c, 0xa5,
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0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30,
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0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
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},
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},
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{
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.pixel_clock = 27027000,
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.conf = {
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0x01, 0x51, 0x2d, 0x72, 0x64, 0x09, 0x88, 0xc3,
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0x71, 0x50, 0x24, 0x14, 0x24, 0x0f, 0x7c, 0xa5,
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0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30,
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0x28, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
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},
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},
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{
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.pixel_clock = 40000000,
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.conf = {
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0x01, 0x51, 0x32, 0x55, 0x01, 0x00, 0x88, 0x02,
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0x4d, 0x50, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
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0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
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0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
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},
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},
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{
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.pixel_clock = 50000000,
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.conf = {
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0x01, 0x51, 0x34, 0x40, 0x64, 0x09, 0x88, 0xc3,
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0x3d, 0x50, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
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0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
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0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
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},
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},
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{
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.pixel_clock = 65000000,
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.conf = {
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0x01, 0x51, 0x36, 0x31, 0x40, 0x10, 0x04, 0xc6,
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0x2e, 0xe8, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
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0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
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0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
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},
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},
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{
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.pixel_clock = 74176000,
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.conf = {
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0x01, 0x51, 0x3E, 0x35, 0x5B, 0xDE, 0x88, 0x42,
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0x53, 0x51, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
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0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
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0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
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},
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},
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{
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.pixel_clock = 74250000,
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.conf = {
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0x01, 0x51, 0x3E, 0x35, 0x40, 0xF0, 0x88, 0xC2,
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0x52, 0x51, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
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0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
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0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
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},
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},
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{
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.pixel_clock = 108000000,
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.conf = {
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0x01, 0x51, 0x2d, 0x15, 0x01, 0x00, 0x88, 0x02,
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0x72, 0x52, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
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0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
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0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
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},
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},
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{
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.pixel_clock = 148500000,
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.conf = {
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0x01, 0x51, 0x1f, 0x00, 0x40, 0xf8, 0x88, 0xc1,
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0x52, 0x52, 0x24, 0x0c, 0x24, 0x0f, 0x7c, 0xa5,
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0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30,
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0x08, 0x10, 0x01, 0x01, 0x48, 0x4a, 0x00, 0x40,
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},
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},
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};
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static const char * const hdmi_clk_gates4[] = {
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"hdmi", "sclk_hdmi"
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};
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@ -524,6 +610,15 @@ static const char * const hdmi_clk_muxes4[] = {
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"sclk_pixel", "sclk_hdmiphy", "mout_hdmi"
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};
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static const char * const hdmi_clk_gates5433[] = {
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"hdmi_pclk", "hdmi_i_pclk", "i_tmds_clk", "i_pixel_clk", "i_spdif_clk"
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};
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static const char * const hdmi_clk_muxes5433[] = {
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"oscclk", "tmds_clko", "tmds_clko_user",
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"oscclk", "pixel_clko", "pixel_clko_user"
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};
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static const struct hdmi_driver_data exynos4210_hdmi_driver_data = {
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.type = HDMI_TYPE13,
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.phy_confs = INIT_ARRAY_SPEC(hdmiphy_v13_configs),
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@ -546,6 +641,15 @@ static const struct hdmi_driver_data exynos5420_hdmi_driver_data = {
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.clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes4),
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};
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static const struct hdmi_driver_data exynos5433_hdmi_driver_data = {
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.type = HDMI_TYPE14,
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.is_apb_phy = 1,
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.has_sysreg = 1,
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.phy_confs = INIT_ARRAY_SPEC(hdmiphy_5433_configs),
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.clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates5433),
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.clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes5433),
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};
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static inline u32 hdmi_map_reg(struct hdmi_context *hdata, u32 reg_id)
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{
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if ((reg_id & 0xffff0000) == HDMI_MAPPED_BASE)
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@ -1539,6 +1643,8 @@ static void hdmi_v14_mode_apply(struct hdmi_context *hdata)
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hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, m->htotal - m->hdisplay);
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hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay);
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hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal);
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if (hdata->drv_data == &exynos5433_hdmi_driver_data)
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hdmi_reg_writeb(hdata, HDMI_TG_DECON_EN, 1);
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}
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static void hdmi_mode_apply(struct hdmi_context *hdata)
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@ -1563,6 +1669,14 @@ static void hdmiphy_conf_reset(struct hdmi_context *hdata)
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usleep_range(10000, 12000);
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}
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static void hdmiphy_enable_mode_set(struct hdmi_context *hdata, bool enable)
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{
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u8 v = enable ? HDMI_PHY_ENABLE_MODE_SET : HDMI_PHY_DISABLE_MODE_SET;
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if (hdata->drv_data == &exynos5433_hdmi_driver_data)
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writel(v, hdata->regs_hdmiphy + HDMIPHY5433_MODE_SET_DONE);
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}
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static void hdmiphy_conf_apply(struct hdmi_context *hdata)
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{
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int ret;
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@ -1574,12 +1688,14 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata)
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return;
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}
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hdmiphy_enable_mode_set(hdata, true);
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ret = hdmiphy_reg_write_buf(hdata, 0,
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hdata->drv_data->phy_confs.data[i].conf, 32);
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if (ret) {
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DRM_ERROR("failed to configure hdmiphy\n");
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return;
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}
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hdmiphy_enable_mode_set(hdata, false);
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usleep_range(10000, 12000);
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}
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@ -1612,6 +1728,15 @@ static void hdmi_mode_set(struct drm_encoder *encoder,
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hdata->cea_video_id = drm_match_cea_mode(mode);
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}
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static void hdmi_set_refclk(struct hdmi_context *hdata, bool on)
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{
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if (!hdata->sysreg)
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return;
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regmap_update_bits(hdata->sysreg, EXYNOS5433_SYSREG_DISP_HDMI_PHY,
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SYSREG_HDMI_REFCLK_INT_CLK, on ? ~0 : 0);
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}
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static void hdmi_enable(struct drm_encoder *encoder)
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{
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struct hdmi_context *hdata = encoder_to_hdmi(encoder);
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@ -1627,6 +1752,8 @@ static void hdmi_enable(struct drm_encoder *encoder)
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regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
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PMU_HDMI_PHY_ENABLE_BIT, 1);
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hdmi_set_refclk(hdata, true);
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hdmi_conf_apply(hdata);
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hdata->powered = true;
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@ -1659,6 +1786,8 @@ static void hdmi_disable(struct drm_encoder *encoder)
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cancel_delayed_work(&hdata->hotplug_work);
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hdmi_set_refclk(hdata, false);
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regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
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PMU_HDMI_PHY_ENABLE_BIT, 0);
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@ -1813,6 +1942,9 @@ static struct of_device_id hdmi_match_types[] = {
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}, {
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.compatible = "samsung,exynos5420-hdmi",
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.data = &exynos5420_hdmi_driver_data,
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}, {
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.compatible = "samsung,exynos5433-hdmi",
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.data = &exynos5433_hdmi_driver_data,
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}, {
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/* end node */
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}
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@ -1980,6 +2112,16 @@ out_get_phy_port:
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goto err_hdmiphy;
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}
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if (hdata->drv_data->has_sysreg) {
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hdata->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
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"samsung,sysreg-phandle");
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if (IS_ERR(hdata->sysreg)) {
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DRM_ERROR("sysreg regmap lookup failed.\n");
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ret = -EPROBE_DEFER;
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goto err_hdmiphy;
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}
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}
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pm_runtime_enable(dev);
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ret = component_add(&pdev->dev, &hdmi_component_ops);
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@ -586,10 +586,12 @@
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#define HDMI_TG_VACT_ST4_L HDMI_TG_BASE(0x0070)
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#define HDMI_TG_VACT_ST4_H HDMI_TG_BASE(0x0074)
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#define HDMI_TG_3D HDMI_TG_BASE(0x00F0)
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#define HDMI_TG_DECON_EN HDMI_TG_BASE(0x01e0)
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/* HDMI PHY Registers Offsets*/
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#define HDMIPHY_POWER (0x74 >> 2)
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#define HDMIPHY_MODE_SET_DONE (0x7c >> 2)
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#define HDMIPHY_POWER 0x74
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#define HDMIPHY_MODE_SET_DONE 0x7c
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#define HDMIPHY5433_MODE_SET_DONE 0x84
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/* HDMI PHY Values */
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#define HDMI_PHY_POWER_ON 0x80
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@ -603,4 +605,7 @@
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#define PMU_HDMI_PHY_CONTROL 0x700
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#define PMU_HDMI_PHY_ENABLE_BIT BIT(0)
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#define EXYNOS5433_SYSREG_DISP_HDMI_PHY 0x1008
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#define SYSREG_HDMI_REFCLK_INT_CLK 1
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#endif /* SAMSUNG_REGS_HDMI_H */
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