drm/amdgpu: add some required DCE6 registers (v7)
To help with the DC port. v2: add missing masks, add additional registers v3: more updates v4: fix accidently dropped changes v5: add missing nb pstate mask v6: add vblank, vline masks v7: add SCL_HORZ_FILTER_INIT regs Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -4444,14 +4444,90 @@
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/* Registers that spilled out of sid.h */
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#define mmDATA_FORMAT 0x1AC0
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#define mmLB0_DATA_FORMAT 0x1AC0
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#define mmLB1_DATA_FORMAT 0x1DC0
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#define mmLB2_DATA_FORMAT 0x40C0
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#define mmLB3_DATA_FORMAT 0x43C0
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#define mmLB4_DATA_FORMAT 0x46C0
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#define mmLB5_DATA_FORMAT 0x49C0
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#define mmDESKTOP_HEIGHT 0x1AC1
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#define mmLB0_DESKTOP_HEIGHT 0x1AC1
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#define mmLB1_DESKTOP_HEIGHT 0x1DC1
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#define mmLB2_DESKTOP_HEIGHT 0x40C1
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#define mmLB3_DESKTOP_HEIGHT 0x43C1
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#define mmLB4_DESKTOP_HEIGHT 0x46C1
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#define mmLB5_DESKTOP_HEIGHT 0x49C1
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#define mmDC_LB_MEMORY_SPLIT 0x1AC3
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#define mmLB0_DC_LB_MEMORY_SPLIT 0x1AC3
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#define mmLB1_DC_LB_MEMORY_SPLIT 0x1DC3
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#define mmLB2_DC_LB_MEMORY_SPLIT 0x40C3
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#define mmLB3_DC_LB_MEMORY_SPLIT 0x43C3
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#define mmLB4_DC_LB_MEMORY_SPLIT 0x46C3
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#define mmLB5_DC_LB_MEMORY_SPLIT 0x49C3
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#define mmDC_LB_MEM_SIZE 0x1AC4
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#define mmLB0_DC_LB_MEM_SIZE 0x1AC4
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#define mmLB1_DC_LB_MEM_SIZE 0x1DC4
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#define mmLB2_DC_LB_MEM_SIZE 0x40C4
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#define mmLB3_DC_LB_MEM_SIZE 0x43C4
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#define mmLB4_DC_LB_MEM_SIZE 0x46C4
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#define mmLB5_DC_LB_MEM_SIZE 0x49C4
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#define mmPRIORITY_A_CNT 0x1AC6
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#define mmLB0_PRIORITY_A_CNT 0x1AC6
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#define mmLB1_PRIORITY_A_CNT 0x1DC6
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#define mmLB2_PRIORITY_A_CNT 0x40C6
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#define mmLB3_PRIORITY_A_CNT 0x43C6
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#define mmLB4_PRIORITY_A_CNT 0x46C6
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#define mmLB5_PRIORITY_A_CNT 0x49C6
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#define mmPRIORITY_B_CNT 0x1AC7
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#define mmLB0_PRIORITY_B_CNT 0x1AC7
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#define mmLB1_PRIORITY_B_CNT 0x1DC7
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#define mmLB2_PRIORITY_B_CNT 0x40C7
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#define mmLB3_PRIORITY_B_CNT 0x43C7
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#define mmLB4_PRIORITY_B_CNT 0x46C7
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#define mmLB5_PRIORITY_B_CNT 0x49C7
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#define mmDPG_PIPE_ARBITRATION_CONTROL3 0x1B32
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#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL3 0x1B32
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#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL3 0x1E32
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#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL3 0x4132
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#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL3 0x4432
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#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL3 0x4732
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#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL3 0x4A32
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#define mmINT_MASK 0x1AD0
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#define mmLB0_INT_MASK 0x1AD0
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#define mmLB1_INT_MASK 0x1DD0
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#define mmLB2_INT_MASK 0x40D0
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#define mmLB3_INT_MASK 0x43D0
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#define mmLB4_INT_MASK 0x46D0
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#define mmLB5_INT_MASK 0x49D0
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#define mmVLINE_STATUS 0x1AEE
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#define mmLB0_VLINE_STATUS 0x1AEE
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#define mmLB1_VLINE_STATUS 0x1DEE
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#define mmLB2_VLINE_STATUS 0x40EE
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#define mmLB3_VLINE_STATUS 0x43EE
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#define mmLB4_VLINE_STATUS 0x46EE
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#define mmLB5_VLINE_STATUS 0x49EE
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#define mmVBLANK_STATUS 0x1AEF
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#define mmLB0_VBLANK_STATUS 0x1AEF
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#define mmLB1_VBLANK_STATUS 0x1DEF
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#define mmLB2_VBLANK_STATUS 0x40EF
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#define mmLB3_VBLANK_STATUS 0x43EF
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#define mmLB4_VBLANK_STATUS 0x46EF
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#define mmLB5_VBLANK_STATUS 0x49EF
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#define mmSCL_HORZ_FILTER_INIT_RGB_LUMA 0x1B4C
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#define mmSCL0_SCL_HORZ_FILTER_INIT_RGB_LUMA 0x1B4C
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#define mmSCL1_SCL_HORZ_FILTER_INIT_RGB_LUMA 0x1E4C
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#define mmSCL2_SCL_HORZ_FILTER_INIT_RGB_LUMA 0x414C
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#define mmSCL3_SCL_HORZ_FILTER_INIT_RGB_LUMA 0x444C
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#define mmSCL4_SCL_HORZ_FILTER_INIT_RGB_LUMA 0x474C
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#define mmSCL5_SCL_HORZ_FILTER_INIT_RGB_LUMA 0x4A4C
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#define mmSCL_HORZ_FILTER_INIT_CHROMA 0x1B4D
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#define mmSCL0_SCL_HORZ_FILTER_INIT_CHROMA 0x1B4D
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#define mmSCL1_SCL_HORZ_FILTER_INIT_CHROMA 0x1E4D
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#define mmSCL2_SCL_HORZ_FILTER_INIT_CHROMA 0x414D
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#define mmSCL3_SCL_HORZ_FILTER_INIT_CHROMA 0x444D
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#define mmSCL4_SCL_HORZ_FILTER_INIT_CHROMA 0x474D
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#define mmSCL5_SCL_HORZ_FILTER_INIT_CHROMA 0x4A4D
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#endif
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@ -2076,6 +2076,8 @@
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#define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0x0000000c
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#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
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#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x00000004
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#define CRTC_CONTROL__CRTC_PREFETCH_EN_MASK 0x10000000L
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#define CRTC_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x0000001c
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#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
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#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x00000000
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#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001eL
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@ -6364,6 +6366,8 @@
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#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x00000000
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#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000L
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#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x00000010
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#define DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK_MASK 0x00030000L
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#define DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK__SHIFT 0x00000010
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#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x00000001L
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#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x00000000
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#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x00000010L
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@ -6384,6 +6388,8 @@
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#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x00000008
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#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
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#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x00000004
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#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00003000L
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#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x0000000c
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#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000L
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#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x00000010
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#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x00000001L
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#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x00000008
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#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
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#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x00000000
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#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00003000L
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#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0000000c
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#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000L
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#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x00000010
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#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
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#define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x00000008
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#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0x000c0000L
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#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x00000012
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#define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0x00f00000L
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#define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x00000014
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#define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x0000000cL
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#define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x00000002
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#define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000L
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@ -9835,4 +9845,98 @@
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#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
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#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
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// DATA_FORMAT
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#define DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L
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#define DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x00000000
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#define DATA_FORMAT__RESET_REQ_AT_EOL_MASK 0x00000010L
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#define DATA_FORMAT__RESET_REQ_AT_EOL__SHIFT 0x00000004
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#define DATA_FORMAT__PREFETCH_MASK 0x00001000L
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#define DATA_FORMAT__PREFETCH__SHIFT 0x0000000c
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#define DATA_FORMAT__SOF_READ_PT_MASK 0x001f0000L
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#define DATA_FORMAT__SOF_READ_PT__SHIFT 0x00000010
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#define DATA_FORMAT__REQUEST_MODE_MASK 0x03000000L
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#define DATA_FORMAT__REQUEST_MODE__SHIFT 0x00000018
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#define DATA_FORMAT__ALLOW_REQ_MODE_1_2_MASK 0x10000000L
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#define DATA_FORMAT__ALLOW_REQ_MODE_1_2__SHIFT 0x0000001c
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// DC_LB_MEMORY_SPLIT
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#define DC_LB_MEMORY_SPLIT__LB_NUM_PARTITIONS_MASK 0x000f0000L
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#define DC_LB_MEMORY_SPLIT__LB_NUM_PARTITIONS__SHIFT 0x00000010
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#define DC_LB_MEMORY_SPLIT__DC_LB_MEMORY_CONFIG_MASK 0x00300000L
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#define DC_LB_MEMORY_SPLIT__DC_LB_MEMORY_CONFIG__SHIFT 0x00000014
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// DC_LB_MEM_SIZE
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#define DC_LB_MEM_SIZE__DC_LB_MEM_SIZE_MASK 0x000007ffL
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#define DC_LB_MEM_SIZE__DC_LB_MEM_SIZE__SHIFT 0x00000000
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// SCL_TAP_CONTROL
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#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
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#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x00000000
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#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000f00L
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#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x00000008
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// INT_MASK
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#define INT_MASK__VBLANK_INT_MASK 0x00000001L
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#define INT_MASK__VBLANK_INT__SHIFT 0x00000000
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#define INT_MASK__VLINE_INT_MASK 0x00000010L
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#define INT_MASK__VLINE_INT__SHIFT 0x00000004
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// PRIORITY_A_CNT
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#define PRIORITY_A_CNT__PRIORITY_MARK_A_MASK 0x00007fffL
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#define PRIORITY_A_CNT__PRIORITY_MARK_A__SHIFT 0x00000000
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#define PRIORITY_A_CNT__PRIORITY_A_OFF_MASK 0x00010000L
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#define PRIORITY_A_CNT__PRIORITY_A_OFF__SHIFT 0x00000010
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#define PRIORITY_A_CNT__PRIORITY_A_ALWAYS_ON_MASK 0x00100000L
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#define PRIORITY_A_CNT__PRIORITY_A_ALWAYS_ON__SHIFT 0x00000014
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#define PRIORITY_A_CNT__PRIORITY_A_FORCE_MASK_MASK 0x01000000L
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#define PRIORITY_A_CNT__PRIORITY_A_FORCE_MASK__SHIFT 0x00000018
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// PRIORITY_B_CNT
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#define PRIORITY_B_CNT__PRIORITY_MARK_B_MASK 0x00007fffL
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#define PRIORITY_B_CNT__PRIORITY_MARK_B__SHIFT 0x00000000
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#define PRIORITY_B_CNT__PRIORITY_B_OFF_MASK 0x00010000L
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#define PRIORITY_B_CNT__PRIORITY_B_OFF__SHIFT 0x00000010
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#define PRIORITY_B_CNT__PRIORITY_B_ALWAYS_ON_MASK 0x00100000L
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#define PRIORITY_B_CNT__PRIORITY_B_ALWAYS_ON__SHIFT 0x00000014
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#define PRIORITY_B_CNT__PRIORITY_B_FORCE_MASK_MASK 0x01000000L
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#define PRIORITY_B_CNT__PRIORITY_B_FORCE_MASK__SHIFT 0x00000018
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// VLINE_STATUS
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#define VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
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#define VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x00000000
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#define VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
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#define VLINE_STATUS__VLINE_ACK__SHIFT 0x00000004
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#define VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
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#define VLINE_STATUS__VLINE_STAT__SHIFT 0x0000000c
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#define VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
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#define VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x00000010
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#define VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
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#define VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x00000011
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// VBLANK_STATUS
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#define VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
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#define VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x00000000
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#define VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
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#define VBLANK_STATUS__VBLANK_ACK__SHIFT 0x00000004
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#define VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
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#define VBLANK_STATUS__VBLANK_STAT__SHIFT 0x0000000c
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#define VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
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#define VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x00000010
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#define VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
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#define VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x00000011
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// SCL_HORZ_FILTER_INIT_RGB_LUMA
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#define SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_FRAC_RGB_Y_MASK 0x0000ffffL
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#define SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_FRAC_RGB_Y__SHIFT 0x00000000
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#define SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_INT_RGB_Y_MASK 0x000f0000L
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#define SCL_HORZ_FILTER_INIT_RGB_LUMA__SCL_H_INIT_INT_RGB_Y__SHIFT 0x00000010
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// SCL_HORZ_FILTER_INIT_CHROMA
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#define SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_FRAC_CBCR_MASK 0x0000ffffL
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#define SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_FRAC_CBCR__SHIFT 0x00000000
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#define SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_INT_CBCR_MASK 0x00070000L
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#define SCL_HORZ_FILTER_INIT_CHROMA__SCL_H_INIT_INT_CBCR__SHIFT 0x00000010
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#endif
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