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arm64: dts: qcom: msm8998: Add DMA to I2C hosts 

Add DMA properties to I2C hosts to allow for DMA transfers.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210109163001.146867-3-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Konrad Dybcio 2021-01-09 17:29:56 +01:00 committed by Bjorn Andersson
parent 03e6cb3d8a
commit 6845359eea
1 changed files with 37 additions and 0 deletions
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37
arch/arm64/boot/dts/qcom/msm8998.dtsi
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@ -1893,6 +1893,8 @@
clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
dma-names = "tx", "rx";
clock-frequency = <400000>;
status = "disabled";
@ -1908,6 +1910,8 @@
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
dma-names = "tx", "rx";
clock-frequency = <400000>;
status = "disabled";
@ -1923,6 +1927,8 @@
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
dma-names = "tx", "rx";
clock-frequency = <400000>;
status = "disabled";
@ -1938,6 +1944,8 @@
clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
dma-names = "tx", "rx";
clock-frequency = <400000>;
status = "disabled";
@ -1953,6 +1961,8 @@
clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
dma-names = "tx", "rx";
clock-frequency = <400000>;
status = "disabled";
@ -1968,6 +1978,8 @@
clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
dma-names = "tx", "rx";
clock-frequency = <400000>;
status = "disabled";
@ -1975,6 +1987,19 @@
#size-cells = <0>;
};
blsp2_dma: dma@c184000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x0c184000 0x25000>;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
qcom,controlled-remotely;
num-channels = <18>;
qcom,num-ees = <4>;
};
blsp2_uart1: serial@c1b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x0c1b0000 0x1000>;
@ -1993,6 +2018,8 @@
clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
dma-names = "tx", "rx";
clock-frequency = <400000>;
status = "disabled";
@ -2008,6 +2035,8 @@
clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
dma-names = "tx", "rx";
clock-frequency = <400000>;
status = "disabled";
@ -2023,6 +2052,8 @@
clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
dma-names = "tx", "rx";
clock-frequency = <400000>;
status = "disabled";
@ -2038,6 +2069,8 @@
clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
dma-names = "tx", "rx";
clock-frequency = <400000>;
status = "disabled";
@ -2053,6 +2086,8 @@
clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
dma-names = "tx", "rx";
clock-frequency = <400000>;
status = "disabled";
@ -2068,6 +2103,8 @@
clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
dma-names = "tx", "rx";
clock-frequency = <400000>;
status = "disabled";