drm/i915: Add pre/post plane updates for SAGV
Lets have a unified way to handle SAGV changes, espoecially considering the upcoming Gen12 changes. Current "standard" way of doing this in commit_tail is pre/post plane updates, when everything which has to be forbidden and not supported in new config has to be restricted before update and relaxed after plane update. v2: - Removed unneeded returns(Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200415143911.10244-5-stanislav.lisovskiy@intel.com
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@ -15354,12 +15354,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
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intel_set_cdclk_pre_plane_update(state);
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intel_set_cdclk_pre_plane_update(state);
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/*
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intel_sagv_pre_plane_update(state);
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* SKL workaround: bspec recommends we disable the SAGV when we
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* have more then one pipe enabled
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*/
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if (!intel_can_enable_sagv(state))
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intel_disable_sagv(dev_priv);
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intel_modeset_verify_disabled(dev_priv, state);
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intel_modeset_verify_disabled(dev_priv, state);
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}
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}
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@ -15456,11 +15451,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
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intel_check_cpu_fifo_underruns(dev_priv);
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intel_check_cpu_fifo_underruns(dev_priv);
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intel_check_pch_fifo_underruns(dev_priv);
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intel_check_pch_fifo_underruns(dev_priv);
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if (state->modeset)
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if (state->modeset) {
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intel_verify_planes(state);
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intel_verify_planes(state);
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if (state->modeset && intel_can_enable_sagv(state))
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intel_sagv_post_plane_update(state);
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intel_enable_sagv(dev_priv);
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}
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drm_atomic_helper_commit_hw_done(&state->base);
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drm_atomic_helper_commit_hw_done(&state->base);
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@ -3757,6 +3757,22 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
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return 0;
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return 0;
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}
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}
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void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
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{
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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if (!intel_can_enable_sagv(state))
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intel_disable_sagv(dev_priv);
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}
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void intel_sagv_post_plane_update(struct intel_atomic_state *state)
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{
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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if (intel_can_enable_sagv(state))
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intel_enable_sagv(dev_priv);
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}
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static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
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static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
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{
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{
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struct drm_device *dev = crtc_state->uapi.crtc->dev;
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struct drm_device *dev = crtc_state->uapi.crtc->dev;
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@ -44,6 +44,8 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
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bool intel_can_enable_sagv(struct intel_atomic_state *state);
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bool intel_can_enable_sagv(struct intel_atomic_state *state);
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int intel_enable_sagv(struct drm_i915_private *dev_priv);
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int intel_enable_sagv(struct drm_i915_private *dev_priv);
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int intel_disable_sagv(struct drm_i915_private *dev_priv);
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int intel_disable_sagv(struct drm_i915_private *dev_priv);
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void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
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void intel_sagv_post_plane_update(struct intel_atomic_state *state);
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bool skl_wm_level_equals(const struct skl_wm_level *l1,
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bool skl_wm_level_equals(const struct skl_wm_level *l1,
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const struct skl_wm_level *l2);
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const struct skl_wm_level *l2);
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bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
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bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
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