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drm/amd/pp: Export registers for read vddc on VI/Vega10 

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2018-01-02 14:06:05 +08:00 committed by Alex Deucher
parent 039fdc94c1
commit 680731ade5
4 changed files with 11 additions and 2 deletions
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1
drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h
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@ -1246,5 +1246,6 @@
#define ixGC_CAC_OVRD_CU 0xe7
#define ixCURRENT_PG_STATUS 0xc020029c
#define ixCURRENT_PG_STATUS_APU 0xd020029c
#define ixPWR_SVI2_STATUS 0xC0200294
#endif /* SMU_7_1_3_D_H */

6
drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h
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@ -6078,6 +6078,8 @@
#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x10
#define CURRENT_PG_STATUS__VCE_PG_STATUS_MASK 0x00000002
#define CURRENT_PG_STATUS__UVD_PG_STATUS_MASK 0x00000004
#define PWR_SVI2_STATUS__PLANE1_VID_MASK 0x000000ff
#define PWR_SVI2_STATUS__PLANE1_VID__SHIFT 0x00000000
#define PWR_SVI2_STATUS__PLANE2_VID_MASK 0x0000ff00
#define PWR_SVI2_STATUS__PLANE2_VID__SHIFT 0x00000008
#endif /* SMU_7_1_3_SH_MASK_H */

3
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h
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@ -172,4 +172,7 @@
#define mmROM_SW_DATA_64 0x006d
#define mmROM_SW_DATA_64_BASE_IDX 0
#define mmSMUSVI0_PLANE0_CURRENTVID_BASE_IDX 0
#define mmSMUSVI0_PLANE0_CURRENTVID 0x0013
#endif

3
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h
View File

@ -254,5 +254,8 @@
//ROM_SW_DATA_64
#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0
#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xFFFFFFFFL
/* SMUSVI0_PLANE0_CURRENTVID */
#define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT 0x18
#define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK 0xFF000000L
#endif