dmaengine: add Qualcomm Technologies HIDMA channel driver
This patch adds support for hidma engine. The driver consists of two logical blocks. The DMA engine interface and the low-level interface. The hardware only supports memcpy/memset and this driver only support memcpy interface. HW and driver doesn't support slave interface. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Sinan Kaya
Vinod Koul
parent
7f8f209fd6
commit
67a2003e06
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@ -17,3 +17,13 @@ config QCOM_HIDMA_MGMT
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start managing the channels. In a virtualized environment,
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the guest OS would run QCOM_HIDMA channel driver and the
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host would run the QCOM_HIDMA_MGMT management driver.
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config QCOM_HIDMA
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tristate "Qualcomm Technologies HIDMA Channel support"
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select DMA_ENGINE
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help
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Enable support for the Qualcomm Technologies HIDMA controller.
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The HIDMA controller supports optimized buffer copies
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(user to kernel, kernel to kernel, etc.). It only supports
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memcpy interface. The core is not intended for general
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purpose slave DMA.
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@ -0,0 +1,706 @@
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/*
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* Qualcomm Technologies HIDMA DMA engine interface
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*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* Copyright (C) Freescale Semicondutor, Inc. 2007, 2008.
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* Copyright (C) Semihalf 2009
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* Copyright (C) Ilya Yanok, Emcraft Systems 2010
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* Copyright (C) Alexander Popov, Promcontroller 2014
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*
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* Written by Piotr Ziecik <kosmo@semihalf.com>. Hardware description
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* (defines, structures and comments) was taken from MPC5121 DMA driver
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* written by Hongjun Chen <hong-jun.chen@freescale.com>.
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*
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* Approved as OSADL project by a majority of OSADL members and funded
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* by OSADL membership fees in 2009; for details see www.osadl.org.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called COPYING.
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*/
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/* Linux Foundation elects GPLv2 license only. */
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/of_dma.h>
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#include <linux/property.h>
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#include <linux/delay.h>
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#include <linux/acpi.h>
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#include <linux/irq.h>
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#include <linux/atomic.h>
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#include <linux/pm_runtime.h>
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#include "../dmaengine.h"
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#include "hidma.h"
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/*
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* Default idle time is 2 seconds. This parameter can
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* be overridden by changing the following
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* /sys/bus/platform/devices/QCOM8061:<xy>/power/autosuspend_delay_ms
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* during kernel boot.
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*/
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#define HIDMA_AUTOSUSPEND_TIMEOUT 2000
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#define HIDMA_ERR_INFO_SW 0xFF
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#define HIDMA_ERR_CODE_UNEXPECTED_TERMINATE 0x0
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#define HIDMA_NR_DEFAULT_DESC 10
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static inline struct hidma_dev *to_hidma_dev(struct dma_device *dmadev)
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{
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return container_of(dmadev, struct hidma_dev, ddev);
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}
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static inline
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struct hidma_dev *to_hidma_dev_from_lldev(struct hidma_lldev **_lldevp)
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{
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return container_of(_lldevp, struct hidma_dev, lldev);
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}
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static inline struct hidma_chan *to_hidma_chan(struct dma_chan *dmach)
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{
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return container_of(dmach, struct hidma_chan, chan);
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}
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static inline
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struct hidma_desc *to_hidma_desc(struct dma_async_tx_descriptor *t)
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{
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return container_of(t, struct hidma_desc, desc);
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}
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static void hidma_free(struct hidma_dev *dmadev)
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{
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INIT_LIST_HEAD(&dmadev->ddev.channels);
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}
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static unsigned int nr_desc_prm;
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module_param(nr_desc_prm, uint, 0644);
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MODULE_PARM_DESC(nr_desc_prm, "number of descriptors (default: 0)");
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/* process completed descriptors */
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static void hidma_process_completed(struct hidma_chan *mchan)
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{
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struct dma_device *ddev = mchan->chan.device;
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struct hidma_dev *mdma = to_hidma_dev(ddev);
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struct dma_async_tx_descriptor *desc;
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dma_cookie_t last_cookie;
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struct hidma_desc *mdesc;
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unsigned long irqflags;
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struct list_head list;
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INIT_LIST_HEAD(&list);
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/* Get all completed descriptors */
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spin_lock_irqsave(&mchan->lock, irqflags);
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list_splice_tail_init(&mchan->completed, &list);
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spin_unlock_irqrestore(&mchan->lock, irqflags);
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/* Execute callbacks and run dependencies */
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list_for_each_entry(mdesc, &list, node) {
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enum dma_status llstat;
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desc = &mdesc->desc;
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spin_lock_irqsave(&mchan->lock, irqflags);
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dma_cookie_complete(desc);
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spin_unlock_irqrestore(&mchan->lock, irqflags);
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llstat = hidma_ll_status(mdma->lldev, mdesc->tre_ch);
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if (desc->callback && (llstat == DMA_COMPLETE))
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desc->callback(desc->callback_param);
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last_cookie = desc->cookie;
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dma_run_dependencies(desc);
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}
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/* Free descriptors */
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spin_lock_irqsave(&mchan->lock, irqflags);
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list_splice_tail_init(&list, &mchan->free);
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spin_unlock_irqrestore(&mchan->lock, irqflags);
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}
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/*
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* Called once for each submitted descriptor.
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* PM is locked once for each descriptor that is currently
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* in execution.
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*/
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static void hidma_callback(void *data)
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{
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struct hidma_desc *mdesc = data;
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struct hidma_chan *mchan = to_hidma_chan(mdesc->desc.chan);
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struct dma_device *ddev = mchan->chan.device;
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struct hidma_dev *dmadev = to_hidma_dev(ddev);
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unsigned long irqflags;
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bool queued = false;
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spin_lock_irqsave(&mchan->lock, irqflags);
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if (mdesc->node.next) {
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/* Delete from the active list, add to completed list */
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list_move_tail(&mdesc->node, &mchan->completed);
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queued = true;
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/* calculate the next running descriptor */
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mchan->running = list_first_entry(&mchan->active,
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struct hidma_desc, node);
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}
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spin_unlock_irqrestore(&mchan->lock, irqflags);
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hidma_process_completed(mchan);
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if (queued) {
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pm_runtime_mark_last_busy(dmadev->ddev.dev);
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pm_runtime_put_autosuspend(dmadev->ddev.dev);
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}
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}
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static int hidma_chan_init(struct hidma_dev *dmadev, u32 dma_sig)
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{
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struct hidma_chan *mchan;
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struct dma_device *ddev;
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mchan = devm_kzalloc(dmadev->ddev.dev, sizeof(*mchan), GFP_KERNEL);
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if (!mchan)
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return -ENOMEM;
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ddev = &dmadev->ddev;
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mchan->dma_sig = dma_sig;
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mchan->dmadev = dmadev;
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mchan->chan.device = ddev;
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dma_cookie_init(&mchan->chan);
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INIT_LIST_HEAD(&mchan->free);
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INIT_LIST_HEAD(&mchan->prepared);
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INIT_LIST_HEAD(&mchan->active);
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INIT_LIST_HEAD(&mchan->completed);
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spin_lock_init(&mchan->lock);
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list_add_tail(&mchan->chan.device_node, &ddev->channels);
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dmadev->ddev.chancnt++;
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return 0;
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}
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static void hidma_issue_task(unsigned long arg)
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{
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struct hidma_dev *dmadev = (struct hidma_dev *)arg;
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pm_runtime_get_sync(dmadev->ddev.dev);
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hidma_ll_start(dmadev->lldev);
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}
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static void hidma_issue_pending(struct dma_chan *dmach)
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{
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struct hidma_chan *mchan = to_hidma_chan(dmach);
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struct hidma_dev *dmadev = mchan->dmadev;
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unsigned long flags;
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int status;
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spin_lock_irqsave(&mchan->lock, flags);
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if (!mchan->running) {
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struct hidma_desc *desc = list_first_entry(&mchan->active,
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struct hidma_desc,
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node);
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mchan->running = desc;
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}
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spin_unlock_irqrestore(&mchan->lock, flags);
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/* PM will be released in hidma_callback function. */
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status = pm_runtime_get(dmadev->ddev.dev);
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if (status < 0)
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tasklet_schedule(&dmadev->task);
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else
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hidma_ll_start(dmadev->lldev);
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}
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static enum dma_status hidma_tx_status(struct dma_chan *dmach,
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dma_cookie_t cookie,
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struct dma_tx_state *txstate)
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{
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struct hidma_chan *mchan = to_hidma_chan(dmach);
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enum dma_status ret;
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ret = dma_cookie_status(dmach, cookie, txstate);
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if (ret == DMA_COMPLETE)
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return ret;
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if (mchan->paused && (ret == DMA_IN_PROGRESS)) {
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unsigned long flags;
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dma_cookie_t runcookie;
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spin_lock_irqsave(&mchan->lock, flags);
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if (mchan->running)
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runcookie = mchan->running->desc.cookie;
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else
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runcookie = -EINVAL;
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if (runcookie == cookie)
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ret = DMA_PAUSED;
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spin_unlock_irqrestore(&mchan->lock, flags);
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}
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return ret;
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}
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/*
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* Submit descriptor to hardware.
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* Lock the PM for each descriptor we are sending.
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*/
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static dma_cookie_t hidma_tx_submit(struct dma_async_tx_descriptor *txd)
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{
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struct hidma_chan *mchan = to_hidma_chan(txd->chan);
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struct hidma_dev *dmadev = mchan->dmadev;
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struct hidma_desc *mdesc;
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unsigned long irqflags;
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dma_cookie_t cookie;
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pm_runtime_get_sync(dmadev->ddev.dev);
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if (!hidma_ll_isenabled(dmadev->lldev)) {
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pm_runtime_mark_last_busy(dmadev->ddev.dev);
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pm_runtime_put_autosuspend(dmadev->ddev.dev);
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return -ENODEV;
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}
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mdesc = container_of(txd, struct hidma_desc, desc);
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spin_lock_irqsave(&mchan->lock, irqflags);
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/* Move descriptor to active */
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list_move_tail(&mdesc->node, &mchan->active);
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/* Update cookie */
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cookie = dma_cookie_assign(txd);
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hidma_ll_queue_request(dmadev->lldev, mdesc->tre_ch);
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spin_unlock_irqrestore(&mchan->lock, irqflags);
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return cookie;
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}
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static int hidma_alloc_chan_resources(struct dma_chan *dmach)
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{
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struct hidma_chan *mchan = to_hidma_chan(dmach);
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struct hidma_dev *dmadev = mchan->dmadev;
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struct hidma_desc *mdesc, *tmp;
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unsigned long irqflags;
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LIST_HEAD(descs);
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unsigned int i;
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int rc = 0;
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if (mchan->allocated)
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return 0;
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/* Alloc descriptors for this channel */
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for (i = 0; i < dmadev->nr_descriptors; i++) {
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mdesc = kzalloc(sizeof(struct hidma_desc), GFP_NOWAIT);
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if (!mdesc) {
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rc = -ENOMEM;
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break;
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}
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dma_async_tx_descriptor_init(&mdesc->desc, dmach);
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mdesc->desc.tx_submit = hidma_tx_submit;
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rc = hidma_ll_request(dmadev->lldev, mchan->dma_sig,
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"DMA engine", hidma_callback, mdesc,
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&mdesc->tre_ch);
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if (rc) {
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dev_err(dmach->device->dev,
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"channel alloc failed at %u\n", i);
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kfree(mdesc);
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break;
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}
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list_add_tail(&mdesc->node, &descs);
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}
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if (rc) {
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/* return the allocated descriptors */
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list_for_each_entry_safe(mdesc, tmp, &descs, node) {
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hidma_ll_free(dmadev->lldev, mdesc->tre_ch);
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kfree(mdesc);
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}
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return rc;
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}
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spin_lock_irqsave(&mchan->lock, irqflags);
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list_splice_tail_init(&descs, &mchan->free);
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mchan->allocated = true;
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spin_unlock_irqrestore(&mchan->lock, irqflags);
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return 1;
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}
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static struct dma_async_tx_descriptor *
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hidma_prep_dma_memcpy(struct dma_chan *dmach, dma_addr_t dest, dma_addr_t src,
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size_t len, unsigned long flags)
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{
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struct hidma_chan *mchan = to_hidma_chan(dmach);
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struct hidma_desc *mdesc = NULL;
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struct hidma_dev *mdma = mchan->dmadev;
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unsigned long irqflags;
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/* Get free descriptor */
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spin_lock_irqsave(&mchan->lock, irqflags);
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if (!list_empty(&mchan->free)) {
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mdesc = list_first_entry(&mchan->free, struct hidma_desc, node);
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list_del(&mdesc->node);
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}
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spin_unlock_irqrestore(&mchan->lock, irqflags);
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if (!mdesc)
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return NULL;
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hidma_ll_set_transfer_params(mdma->lldev, mdesc->tre_ch,
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src, dest, len, flags);
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/* Place descriptor in prepared list */
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spin_lock_irqsave(&mchan->lock, irqflags);
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list_add_tail(&mdesc->node, &mchan->prepared);
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spin_unlock_irqrestore(&mchan->lock, irqflags);
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return &mdesc->desc;
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}
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static int hidma_terminate_channel(struct dma_chan *chan)
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{
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struct hidma_chan *mchan = to_hidma_chan(chan);
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struct hidma_dev *dmadev = to_hidma_dev(mchan->chan.device);
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struct hidma_desc *tmp, *mdesc;
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unsigned long irqflags;
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LIST_HEAD(list);
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int rc;
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pm_runtime_get_sync(dmadev->ddev.dev);
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/* give completed requests a chance to finish */
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hidma_process_completed(mchan);
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spin_lock_irqsave(&mchan->lock, irqflags);
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list_splice_init(&mchan->active, &list);
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list_splice_init(&mchan->prepared, &list);
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list_splice_init(&mchan->completed, &list);
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spin_unlock_irqrestore(&mchan->lock, irqflags);
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/* this suspends the existing transfer */
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rc = hidma_ll_pause(dmadev->lldev);
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if (rc) {
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dev_err(dmadev->ddev.dev, "channel did not pause\n");
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goto out;
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}
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/* return all user requests */
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list_for_each_entry_safe(mdesc, tmp, &list, node) {
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struct dma_async_tx_descriptor *txd = &mdesc->desc;
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dma_async_tx_callback callback = mdesc->desc.callback;
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void *param = mdesc->desc.callback_param;
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dma_descriptor_unmap(txd);
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if (callback)
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callback(param);
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dma_run_dependencies(txd);
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/* move myself to free_list */
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list_move(&mdesc->node, &mchan->free);
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}
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rc = hidma_ll_resume(dmadev->lldev);
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out:
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pm_runtime_mark_last_busy(dmadev->ddev.dev);
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pm_runtime_put_autosuspend(dmadev->ddev.dev);
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return rc;
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}
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static int hidma_terminate_all(struct dma_chan *chan)
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{
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struct hidma_chan *mchan = to_hidma_chan(chan);
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struct hidma_dev *dmadev = to_hidma_dev(mchan->chan.device);
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int rc;
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rc = hidma_terminate_channel(chan);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
/* reinitialize the hardware */
|
||||
pm_runtime_get_sync(dmadev->ddev.dev);
|
||||
rc = hidma_ll_setup(dmadev->lldev);
|
||||
pm_runtime_mark_last_busy(dmadev->ddev.dev);
|
||||
pm_runtime_put_autosuspend(dmadev->ddev.dev);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void hidma_free_chan_resources(struct dma_chan *dmach)
|
||||
{
|
||||
struct hidma_chan *mchan = to_hidma_chan(dmach);
|
||||
struct hidma_dev *mdma = mchan->dmadev;
|
||||
struct hidma_desc *mdesc, *tmp;
|
||||
unsigned long irqflags;
|
||||
LIST_HEAD(descs);
|
||||
|
||||
/* terminate running transactions and free descriptors */
|
||||
hidma_terminate_channel(dmach);
|
||||
|
||||
spin_lock_irqsave(&mchan->lock, irqflags);
|
||||
|
||||
/* Move data */
|
||||
list_splice_tail_init(&mchan->free, &descs);
|
||||
|
||||
/* Free descriptors */
|
||||
list_for_each_entry_safe(mdesc, tmp, &descs, node) {
|
||||
hidma_ll_free(mdma->lldev, mdesc->tre_ch);
|
||||
list_del(&mdesc->node);
|
||||
kfree(mdesc);
|
||||
}
|
||||
|
||||
mchan->allocated = 0;
|
||||
spin_unlock_irqrestore(&mchan->lock, irqflags);
|
||||
}
|
||||
|
||||
static int hidma_pause(struct dma_chan *chan)
|
||||
{
|
||||
struct hidma_chan *mchan;
|
||||
struct hidma_dev *dmadev;
|
||||
|
||||
mchan = to_hidma_chan(chan);
|
||||
dmadev = to_hidma_dev(mchan->chan.device);
|
||||
if (!mchan->paused) {
|
||||
pm_runtime_get_sync(dmadev->ddev.dev);
|
||||
if (hidma_ll_pause(dmadev->lldev))
|
||||
dev_warn(dmadev->ddev.dev, "channel did not stop\n");
|
||||
mchan->paused = true;
|
||||
pm_runtime_mark_last_busy(dmadev->ddev.dev);
|
||||
pm_runtime_put_autosuspend(dmadev->ddev.dev);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hidma_resume(struct dma_chan *chan)
|
||||
{
|
||||
struct hidma_chan *mchan;
|
||||
struct hidma_dev *dmadev;
|
||||
int rc = 0;
|
||||
|
||||
mchan = to_hidma_chan(chan);
|
||||
dmadev = to_hidma_dev(mchan->chan.device);
|
||||
if (mchan->paused) {
|
||||
pm_runtime_get_sync(dmadev->ddev.dev);
|
||||
rc = hidma_ll_resume(dmadev->lldev);
|
||||
if (!rc)
|
||||
mchan->paused = false;
|
||||
else
|
||||
dev_err(dmadev->ddev.dev,
|
||||
"failed to resume the channel");
|
||||
pm_runtime_mark_last_busy(dmadev->ddev.dev);
|
||||
pm_runtime_put_autosuspend(dmadev->ddev.dev);
|
||||
}
|
||||
return rc;
|
||||
}
|
||||
|
||||
static irqreturn_t hidma_chirq_handler(int chirq, void *arg)
|
||||
{
|
||||
struct hidma_lldev *lldev = arg;
|
||||
|
||||
/*
|
||||
* All interrupts are request driven.
|
||||
* HW doesn't send an interrupt by itself.
|
||||
*/
|
||||
return hidma_ll_inthandler(chirq, lldev);
|
||||
}
|
||||
|
||||
static int hidma_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct hidma_dev *dmadev;
|
||||
struct resource *trca_resource;
|
||||
struct resource *evca_resource;
|
||||
int chirq;
|
||||
void __iomem *evca;
|
||||
void __iomem *trca;
|
||||
int rc;
|
||||
|
||||
pm_runtime_set_autosuspend_delay(&pdev->dev, HIDMA_AUTOSUSPEND_TIMEOUT);
|
||||
pm_runtime_use_autosuspend(&pdev->dev);
|
||||
pm_runtime_set_active(&pdev->dev);
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
|
||||
trca_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
trca = devm_ioremap_resource(&pdev->dev, trca_resource);
|
||||
if (IS_ERR(trca)) {
|
||||
rc = -ENOMEM;
|
||||
goto bailout;
|
||||
}
|
||||
|
||||
evca_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
evca = devm_ioremap_resource(&pdev->dev, evca_resource);
|
||||
if (IS_ERR(evca)) {
|
||||
rc = -ENOMEM;
|
||||
goto bailout;
|
||||
}
|
||||
|
||||
/*
|
||||
* This driver only handles the channel IRQs.
|
||||
* Common IRQ is handled by the management driver.
|
||||
*/
|
||||
chirq = platform_get_irq(pdev, 0);
|
||||
if (chirq < 0) {
|
||||
rc = -ENODEV;
|
||||
goto bailout;
|
||||
}
|
||||
|
||||
dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL);
|
||||
if (!dmadev) {
|
||||
rc = -ENOMEM;
|
||||
goto bailout;
|
||||
}
|
||||
|
||||
INIT_LIST_HEAD(&dmadev->ddev.channels);
|
||||
spin_lock_init(&dmadev->lock);
|
||||
dmadev->ddev.dev = &pdev->dev;
|
||||
pm_runtime_get_sync(dmadev->ddev.dev);
|
||||
|
||||
dma_cap_set(DMA_MEMCPY, dmadev->ddev.cap_mask);
|
||||
if (WARN_ON(!pdev->dev.dma_mask)) {
|
||||
rc = -ENXIO;
|
||||
goto dmafree;
|
||||
}
|
||||
|
||||
dmadev->dev_evca = evca;
|
||||
dmadev->evca_resource = evca_resource;
|
||||
dmadev->dev_trca = trca;
|
||||
dmadev->trca_resource = trca_resource;
|
||||
dmadev->ddev.device_prep_dma_memcpy = hidma_prep_dma_memcpy;
|
||||
dmadev->ddev.device_alloc_chan_resources = hidma_alloc_chan_resources;
|
||||
dmadev->ddev.device_free_chan_resources = hidma_free_chan_resources;
|
||||
dmadev->ddev.device_tx_status = hidma_tx_status;
|
||||
dmadev->ddev.device_issue_pending = hidma_issue_pending;
|
||||
dmadev->ddev.device_pause = hidma_pause;
|
||||
dmadev->ddev.device_resume = hidma_resume;
|
||||
dmadev->ddev.device_terminate_all = hidma_terminate_all;
|
||||
dmadev->ddev.copy_align = 8;
|
||||
|
||||
device_property_read_u32(&pdev->dev, "desc-count",
|
||||
&dmadev->nr_descriptors);
|
||||
|
||||
if (!dmadev->nr_descriptors && nr_desc_prm)
|
||||
dmadev->nr_descriptors = nr_desc_prm;
|
||||
|
||||
if (!dmadev->nr_descriptors)
|
||||
dmadev->nr_descriptors = HIDMA_NR_DEFAULT_DESC;
|
||||
|
||||
dmadev->chidx = readl(dmadev->dev_trca + 0x28);
|
||||
|
||||
/* Set DMA mask to 64 bits. */
|
||||
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
|
||||
if (rc) {
|
||||
dev_warn(&pdev->dev, "unable to set coherent mask to 64");
|
||||
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
|
||||
if (rc)
|
||||
goto dmafree;
|
||||
}
|
||||
|
||||
dmadev->lldev = hidma_ll_init(dmadev->ddev.dev,
|
||||
dmadev->nr_descriptors, dmadev->dev_trca,
|
||||
dmadev->dev_evca, dmadev->chidx);
|
||||
if (!dmadev->lldev) {
|
||||
rc = -EPROBE_DEFER;
|
||||
goto dmafree;
|
||||
}
|
||||
|
||||
rc = devm_request_irq(&pdev->dev, chirq, hidma_chirq_handler, 0,
|
||||
"qcom-hidma", dmadev->lldev);
|
||||
if (rc)
|
||||
goto uninit;
|
||||
|
||||
INIT_LIST_HEAD(&dmadev->ddev.channels);
|
||||
rc = hidma_chan_init(dmadev, 0);
|
||||
if (rc)
|
||||
goto uninit;
|
||||
|
||||
rc = dma_async_device_register(&dmadev->ddev);
|
||||
if (rc)
|
||||
goto uninit;
|
||||
|
||||
dmadev->irq = chirq;
|
||||
tasklet_init(&dmadev->task, hidma_issue_task, (unsigned long)dmadev);
|
||||
dev_info(&pdev->dev, "HI-DMA engine driver registration complete\n");
|
||||
platform_set_drvdata(pdev, dmadev);
|
||||
pm_runtime_mark_last_busy(dmadev->ddev.dev);
|
||||
pm_runtime_put_autosuspend(dmadev->ddev.dev);
|
||||
return 0;
|
||||
|
||||
uninit:
|
||||
hidma_ll_uninit(dmadev->lldev);
|
||||
dmafree:
|
||||
if (dmadev)
|
||||
hidma_free(dmadev);
|
||||
bailout:
|
||||
pm_runtime_put_sync(&pdev->dev);
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int hidma_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct hidma_dev *dmadev = platform_get_drvdata(pdev);
|
||||
|
||||
pm_runtime_get_sync(dmadev->ddev.dev);
|
||||
dma_async_device_unregister(&dmadev->ddev);
|
||||
devm_free_irq(dmadev->ddev.dev, dmadev->irq, dmadev->lldev);
|
||||
hidma_ll_uninit(dmadev->lldev);
|
||||
hidma_free(dmadev);
|
||||
|
||||
dev_info(&pdev->dev, "HI-DMA engine removed\n");
|
||||
pm_runtime_put_sync_suspend(&pdev->dev);
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_ACPI)
|
||||
static const struct acpi_device_id hidma_acpi_ids[] = {
|
||||
{"QCOM8061"},
|
||||
{},
|
||||
};
|
||||
#endif
|
||||
|
||||
static const struct of_device_id hidma_match[] = {
|
||||
{.compatible = "qcom,hidma-1.0",},
|
||||
{},
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, hidma_match);
|
||||
|
||||
static struct platform_driver hidma_driver = {
|
||||
.probe = hidma_probe,
|
||||
.remove = hidma_remove,
|
||||
.driver = {
|
||||
.name = "hidma",
|
||||
.of_match_table = hidma_match,
|
||||
.acpi_match_table = ACPI_PTR(hidma_acpi_ids),
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(hidma_driver);
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
/*
|
||||
* Qualcomm Technologies HIDMA data structures
|
||||
*
|
||||
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_HIDMA_H
|
||||
#define QCOM_HIDMA_H
|
||||
|
||||
#include <linux/kfifo.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/dmaengine.h>
|
||||
|
||||
#define TRE_SIZE 32 /* each TRE is 32 bytes */
|
||||
#define TRE_CFG_IDX 0
|
||||
#define TRE_LEN_IDX 1
|
||||
#define TRE_SRC_LOW_IDX 2
|
||||
#define TRE_SRC_HI_IDX 3
|
||||
#define TRE_DEST_LOW_IDX 4
|
||||
#define TRE_DEST_HI_IDX 5
|
||||
|
||||
struct hidma_tx_status {
|
||||
u8 err_info; /* error record in this transfer */
|
||||
u8 err_code; /* completion code */
|
||||
};
|
||||
|
||||
struct hidma_tre {
|
||||
atomic_t allocated; /* if this channel is allocated */
|
||||
bool queued; /* flag whether this is pending */
|
||||
u16 status; /* status */
|
||||
u32 chidx; /* index of the tre */
|
||||
u32 dma_sig; /* signature of the tre */
|
||||
const char *dev_name; /* name of the device */
|
||||
void (*callback)(void *data); /* requester callback */
|
||||
void *data; /* Data associated with this channel*/
|
||||
struct hidma_lldev *lldev; /* lldma device pointer */
|
||||
u32 tre_local[TRE_SIZE / sizeof(u32) + 1]; /* TRE local copy */
|
||||
u32 tre_index; /* the offset where this was written*/
|
||||
u32 int_flags; /* interrupt flags */
|
||||
};
|
||||
|
||||
struct hidma_lldev {
|
||||
bool initialized; /* initialized flag */
|
||||
u8 trch_state; /* trch_state of the device */
|
||||
u8 evch_state; /* evch_state of the device */
|
||||
u8 chidx; /* channel index in the core */
|
||||
u32 nr_tres; /* max number of configs */
|
||||
spinlock_t lock; /* reentrancy */
|
||||
struct hidma_tre *trepool; /* trepool of user configs */
|
||||
struct device *dev; /* device */
|
||||
void __iomem *trca; /* Transfer Channel address */
|
||||
void __iomem *evca; /* Event Channel address */
|
||||
struct hidma_tre
|
||||
**pending_tre_list; /* Pointers to pending TREs */
|
||||
struct hidma_tx_status
|
||||
*tx_status_list; /* Pointers to pending TREs status*/
|
||||
s32 pending_tre_count; /* Number of TREs pending */
|
||||
|
||||
void *tre_ring; /* TRE ring */
|
||||
dma_addr_t tre_ring_handle; /* TRE ring to be shared with HW */
|
||||
u32 tre_ring_size; /* Byte size of the ring */
|
||||
u32 tre_processed_off; /* last processed TRE */
|
||||
|
||||
void *evre_ring; /* EVRE ring */
|
||||
dma_addr_t evre_ring_handle; /* EVRE ring to be shared with HW */
|
||||
u32 evre_ring_size; /* Byte size of the ring */
|
||||
u32 evre_processed_off; /* last processed EVRE */
|
||||
|
||||
u32 tre_write_offset; /* TRE write location */
|
||||
struct tasklet_struct task; /* task delivering notifications */
|
||||
DECLARE_KFIFO_PTR(handoff_fifo,
|
||||
struct hidma_tre *); /* pending TREs FIFO */
|
||||
};
|
||||
|
||||
struct hidma_desc {
|
||||
struct dma_async_tx_descriptor desc;
|
||||
/* link list node for this channel*/
|
||||
struct list_head node;
|
||||
u32 tre_ch;
|
||||
};
|
||||
|
||||
struct hidma_chan {
|
||||
bool paused;
|
||||
bool allocated;
|
||||
char dbg_name[16];
|
||||
u32 dma_sig;
|
||||
|
||||
/*
|
||||
* active descriptor on this channel
|
||||
* It is used by the DMA complete notification to
|
||||
* locate the descriptor that initiated the transfer.
|
||||
*/
|
||||
struct dentry *debugfs;
|
||||
struct dentry *stats;
|
||||
struct hidma_dev *dmadev;
|
||||
struct hidma_desc *running;
|
||||
|
||||
struct dma_chan chan;
|
||||
struct list_head free;
|
||||
struct list_head prepared;
|
||||
struct list_head active;
|
||||
struct list_head completed;
|
||||
|
||||
/* Lock for this structure */
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
struct hidma_dev {
|
||||
int irq;
|
||||
int chidx;
|
||||
u32 nr_descriptors;
|
||||
|
||||
struct hidma_lldev *lldev;
|
||||
void __iomem *dev_trca;
|
||||
struct resource *trca_resource;
|
||||
void __iomem *dev_evca;
|
||||
struct resource *evca_resource;
|
||||
|
||||
/* used to protect the pending channel list*/
|
||||
spinlock_t lock;
|
||||
struct dma_device ddev;
|
||||
|
||||
struct dentry *debugfs;
|
||||
struct dentry *stats;
|
||||
|
||||
/* Task delivering issue_pending */
|
||||
struct tasklet_struct task;
|
||||
};
|
||||
|
||||
int hidma_ll_request(struct hidma_lldev *llhndl, u32 dev_id,
|
||||
const char *dev_name,
|
||||
void (*callback)(void *data), void *data, u32 *tre_ch);
|
||||
|
||||
void hidma_ll_free(struct hidma_lldev *llhndl, u32 tre_ch);
|
||||
enum dma_status hidma_ll_status(struct hidma_lldev *llhndl, u32 tre_ch);
|
||||
bool hidma_ll_isenabled(struct hidma_lldev *llhndl);
|
||||
void hidma_ll_queue_request(struct hidma_lldev *llhndl, u32 tre_ch);
|
||||
void hidma_ll_start(struct hidma_lldev *llhndl);
|
||||
int hidma_ll_pause(struct hidma_lldev *llhndl);
|
||||
int hidma_ll_resume(struct hidma_lldev *llhndl);
|
||||
void hidma_ll_set_transfer_params(struct hidma_lldev *llhndl, u32 tre_ch,
|
||||
dma_addr_t src, dma_addr_t dest, u32 len, u32 flags);
|
||||
int hidma_ll_setup(struct hidma_lldev *lldev);
|
||||
struct hidma_lldev *hidma_ll_init(struct device *dev, u32 max_channels,
|
||||
void __iomem *trca, void __iomem *evca,
|
||||
u8 chidx);
|
||||
int hidma_ll_uninit(struct hidma_lldev *llhndl);
|
||||
irqreturn_t hidma_ll_inthandler(int irq, void *arg);
|
||||
void hidma_cleanup_pending_tre(struct hidma_lldev *llhndl, u8 err_info,
|
||||
u8 err_code);
|
||||
#endif
|
||||
Loading…
Reference in New Issue