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ARM: mx35: Add mx35_revision function to query the silicon revision 

Based on work done earlier by Sascha Hauer

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Eric Bénard <eric@eukrea.com>
[ukl: actually squash the two approaches together]
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Eric Bénard 2010-10-08 16:00:10 +02:00 committed by Sascha Hauer
parent fdb03870a9
commit 67520f3a89
4 changed files with 43 additions and 15 deletions
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3
arch/arm/mach-mx3/clock-imx35.c
View File

@ -535,6 +535,9 @@ int __init mx35_clocks_init()
__raw_writel(cgr2, CCM_BASE + CCM_CGR2);
__raw_writel(cgr3, CCM_BASE + CCM_CGR3);
clk_enable(&iim_clk);
mx35_read_cpu_rev();
#ifdef CONFIG_MXC_USE_EPIT
epit_timer_init(&epit1_clk,
MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);

27
arch/arm/mach-mx3/cpu.c
View File

@ -55,3 +55,30 @@ void __init mx31_read_cpu_rev(void)
printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
}
unsigned int mx35_cpu_rev;
EXPORT_SYMBOL(mx35_cpu_rev);
void __init mx35_read_cpu_rev(void)
{
u32 rev;
char *srev = "unknown";
rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
switch (rev) {
case 0x00:
mx35_cpu_rev = MX3x_CHIP_REV_1_0;
srev = "1.0";
break;
case 0x10:
mx35_cpu_rev = MX3x_CHIP_REV_2_0;
srev = "2.0";
break;
case 0x11:
mx35_cpu_rev = MX3x_CHIP_REV_2_1;
srev = "2.1";
break;
}
printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);
}

18
arch/arm/plat-mxc/include/mach/mx35.h
View File

@ -1,5 +1,6 @@
#ifndef __MACH_MX35_H__
#define __MACH_MX35_H__
/*
* IRAM
*/
@ -66,6 +67,8 @@
#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000)
#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000)
#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000)
#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000)
#define MX35_OTG_BASE_ADDR 0x53ff4000
#define MX35_ROMP_BASE_ADDR 0x60000000
@ -187,20 +190,7 @@
#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */
/* silicon revisions specific to i.MX31 */
#define MX35_CHIP_REV_1_0 0x10
#define MX35_CHIP_REV_1_1 0x11
#define MX35_CHIP_REV_1_2 0x12
#define MX35_CHIP_REV_1_3 0x13
#define MX35_CHIP_REV_2_0 0x20
#define MX35_CHIP_REV_2_1 0x21
#define MX35_CHIP_REV_2_2 0x22
#define MX35_CHIP_REV_2_3 0x23
#define MX35_CHIP_REV_3_0 0x30
#define MX35_CHIP_REV_3_1 0x31
#define MX35_CHIP_REV_3_2 0x32
#define MX35_SYSTEM_REV_MIN MX35_CHIP_REV_1_0
#define MX35_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0
#define MX35_SYSTEM_REV_NUM 3
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS

10
arch/arm/plat-mxc/include/mach/mx3x.h
View File

@ -240,7 +240,7 @@
#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */
/* silicon revisions specific to i.MX31 */
/* silicon revisions specific to i.MX31 and i.MX35 */
#define MX3x_CHIP_REV_1_0 0x10
#define MX3x_CHIP_REV_1_1 0x11
#define MX3x_CHIP_REV_1_2 0x12
@ -267,6 +267,14 @@ static inline int mx31_revision(void)
{
return mx31_cpu_rev;
}
extern unsigned int mx35_cpu_rev;
extern void mx35_read_cpu_rev(void);
static inline int mx35_revision(void)
{
return mx35_cpu_rev;
}
#endif
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS