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drm/i915: PSR: Keep sink state consistent with source 

BSpec recommends to keep the main link state consistent
between the source and the sink. As per that, update
the main link state in sink DPCD register to 'active',
for Valleyview based platforms.

Signed-off-by: Durgadoss R <durgadoss.r@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Tested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Durgadoss R 2015-03-27 17:21:32 +05:30 committed by Daniel Vetter
parent b728d7265b
commit 670b90d20a
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/i915/intel_psr.c
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@ -133,7 +133,7 @@ static void hsw_psr_setup_vsc(struct intel_dp *intel_dp)
static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
{
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
DP_PSR_ENABLE);
DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
}
static void hsw_psr_enable_sink(struct intel_dp *intel_dp)