drm/amd/display: Clean up submit_channel_request
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Vitaly Prosyak <Vitaly.Prosyak@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -198,27 +198,27 @@ static void submit_channel_request(
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((request->type == AUX_TRANSACTION_TYPE_I2C) &&
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((request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
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(request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT)));
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if (REG(AUXN_IMPCAL)) {
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/* clear_aux_error */
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REG_UPDATE_SEQ(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK,
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1,
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0);
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/* clear_aux_error */
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REG_UPDATE_SEQ(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK,
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1,
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0);
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REG_UPDATE_SEQ(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK,
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1,
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0);
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REG_UPDATE_SEQ(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK,
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1,
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0);
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/* force_default_calibrate */
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REG_UPDATE_1BY1_2(AUXN_IMPCAL,
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AUXN_IMPCAL_ENABLE, 1,
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AUXN_IMPCAL_OVERRIDE_ENABLE, 0);
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/* force_default_calibrate */
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REG_UPDATE_1BY1_2(AUXN_IMPCAL,
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AUXN_IMPCAL_ENABLE, 1,
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AUXN_IMPCAL_OVERRIDE_ENABLE, 0);
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/* bug? why AUXN update EN and OVERRIDE_EN 1 by 1 while AUX P toggles OVERRIDE? */
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REG_UPDATE_SEQ(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE,
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1,
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0);
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/* bug? why AUXN update EN and OVERRIDE_EN 1 by 1 while AUX P toggles OVERRIDE? */
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REG_UPDATE_SEQ(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE,
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1,
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0);
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}
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/* set the delay and the number of bytes to write */
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/* The length include
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