dt-bindings: spi: meson: convert to yaml
Now that we have the DT validation in place, let's convert the device tree bindings for the Amlogic SPI controllers over to two separate YAML schemas. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Rob Herring <robh@kernel.org>
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright 2019 BayLibre, SAS
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/spi/amlogic,meson-gx-spicc.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Amlogic Meson SPI Communication Controller
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maintainers:
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- Neil Armstrong <narmstrong@baylibre.com>
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allOf:
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- $ref: "spi-controller.yaml#"
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description: |
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The Meson SPICC is a generic SPI controller for general purpose Full-Duplex
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communications with dedicated 16 words RX/TX PIO FIFOs.
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properties:
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compatible:
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enum:
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- amlogic,meson-gx-spicc # SPICC controller on Amlogic GX and compatible SoCs
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- amlogic,meson-axg-spicc # SPICC controller on Amlogic AXG and compatible SoCs
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interrupts:
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maxItems: 1
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reg:
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maxItems: 1
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resets:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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description: input clock for the baud rate generator
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items:
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- const: core
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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examples:
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- |
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spi@c1108d80 {
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compatible = "amlogic,meson-gx-spicc";
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reg = <0xc1108d80 0x80>;
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interrupts = <112>;
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clocks = <&clk81>;
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clock-names = "core";
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-switch@0 {
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compatible = "micrel,ks8995m";
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spi-max-frequency = <1000000>;
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reg = <0>;
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};
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};
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright 2019 BayLibre, SAS
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/spi/amlogic,meson6-spifc.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Amlogic Meson SPI Flash Controller
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maintainers:
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- Neil Armstrong <narmstrong@baylibre.com>
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allOf:
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- $ref: "spi-controller.yaml#"
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description: |
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The Meson SPIFC is a controller optimized for communication with SPI
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NOR memories, without DMA support and a 64-byte unified transmit /
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receive buffer.
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properties:
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compatible:
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enum:
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- amlogic,meson6-spifc # SPI Flash Controller on Meson6 and compatible SoCs
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- amlogic,meson-gxbb-spifc # SPI Flash Controller on GXBB and compatible SoCs
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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examples:
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- |
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spi@c1108c80 {
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compatible = "amlogic,meson6-spifc";
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reg = <0xc1108c80 0x80>;
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clocks = <&clk81>;
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#address-cells = <1>;
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#size-cells = <0>;
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flash: flash@0 {
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compatible = "spansion,m25p80", "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <40000000>;
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};
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};
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@ -1,55 +0,0 @@
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Amlogic Meson SPI controllers
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* SPIFC (SPI Flash Controller)
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The Meson SPIFC is a controller optimized for communication with SPI
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NOR memories, without DMA support and a 64-byte unified transmit /
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receive buffer.
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Required properties:
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- compatible: should be "amlogic,meson6-spifc" or "amlogic,meson-gxbb-spifc"
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- reg: physical base address and length of the controller registers
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- clocks: phandle of the input clock for the baud rate generator
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- #address-cells: should be 1
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- #size-cells: should be 0
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spi@c1108c80 {
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compatible = "amlogic,meson6-spifc";
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reg = <0xc1108c80 0x80>;
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clocks = <&clk81>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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* SPICC (SPI Communication Controller)
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The Meson SPICC is generic SPI controller for general purpose Full-Duplex
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communications with dedicated 16 words RX/TX PIO FIFOs.
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Required properties:
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- compatible: should be:
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"amlogic,meson-gx-spicc" on Amlogic GX and compatible SoCs.
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"amlogic,meson-axg-spicc" on Amlogic AXG and compatible SoCs
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- reg: physical base address and length of the controller registers
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- interrupts: The interrupt specifier
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- clock-names: Must contain "core"
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- clocks: phandle of the input clock for the baud rate generator
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- #address-cells: should be 1
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- #size-cells: should be 0
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Optional properties:
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- resets: phandle of the internal reset line
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See ../spi/spi-bus.txt for more details on SPI bus master and slave devices
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required and optional properties.
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Example :
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spi@c1108d80 {
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compatible = "amlogic,meson-gx-spicc";
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reg = <0xc1108d80 0x80>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "core";
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clocks = <&clk81>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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