PCI: designware: Fix comment for setting number of lanes
Corrects comment for setting number of lanes. Signed-off-by: Mohit Kumar <mohit.kumar@st.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jg1.han@samsung.com>
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@ -764,7 +764,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
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u32 membase;
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u32 memlimit;
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/* set the number of lines as 4 */
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/* set the number of lanes */
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dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
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val &= ~PORT_LINK_MODE_MASK;
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switch (pp->lanes) {
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