dt-binding base for the new starfive stuff
Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZLhM1gAKCRB4tDGHoIJi 0vskAP4zWCStQWNcwK6Z65JSGKig2z7j1Ij0CWJGEJyK7VhzSAD+O5D0gn1xISEU 99OekMDGxxucSpO4+T0kEQp6jnfqGQk= =WgBZ -----END PGP SIGNATURE----- Merge tag 'clk-starfive-bindings' into riscv-dt-for-next This is the dt-binding base for the new starfive clock stuff, that has been merged into the clk tree by Stephen. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Conor Dooley
commit
66bd0770f3
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@ -0,0 +1,87 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator
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maintainers:
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- Xingyu Wu <xingyu.wu@starfivetech.com>
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properties:
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compatible:
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const: starfive,jh7110-ispcrg
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reg:
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maxItems: 1
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clocks:
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items:
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- description: ISP Top core
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- description: ISP Top Axi
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- description: NOC ISP Bus
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- description: external DVP
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clock-names:
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items:
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- const: isp_top_core
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- const: isp_top_axi
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- const: noc_bus_isp_axi
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- const: dvp_clk
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resets:
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items:
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- description: ISP Top core
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- description: ISP Top Axi
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- description: NOC ISP Bus
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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'#reset-cells':
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const: 1
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description:
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See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
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power-domains:
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maxItems: 1
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description:
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ISP domain power
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- '#clock-cells'
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- '#reset-cells'
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- power-domains
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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#include <dt-bindings/power/starfive,jh7110-pmu.h>
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#include <dt-bindings/reset/starfive,jh7110-crg.h>
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ispcrg: clock-controller@19810000 {
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compatible = "starfive,jh7110-ispcrg";
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reg = <0x19810000 0x10000>;
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clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
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<&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
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<&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
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<&dvp_clk>;
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clock-names = "isp_top_core", "isp_top_axi",
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"noc_bus_isp_axi", "dvp_clk";
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resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
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<&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
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<&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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power-domains = <&pwrc JH7110_PD_ISP>;
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};
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@ -0,0 +1,46 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 PLL Clock Generator
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description:
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These PLLs are high speed, low jitter frequency synthesizers in the JH7110.
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Each PLL works in integer mode or fraction mode, with configuration
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registers in the sys syscon. So the PLLs node should be a child of
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SYS-SYSCON node.
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The formula for calculating frequency is
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Fvco = Fref * (NI + NF) / M / Q1
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maintainers:
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- Xingyu Wu <xingyu.wu@starfivetech.com>
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properties:
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compatible:
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const: starfive,jh7110-pll
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clocks:
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maxItems: 1
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description: Main Oscillator (24 MHz)
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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required:
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- compatible
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- clocks
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller {
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compatible = "starfive,jh7110-pll";
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clocks = <&osc>;
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#clock-cells = <1>;
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};
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@ -0,0 +1,82 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 System-Top-Group Clock and Reset Generator
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maintainers:
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- Xingyu Wu <xingyu.wu@starfivetech.com>
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properties:
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compatible:
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const: starfive,jh7110-stgcrg
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Main Oscillator (24 MHz)
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- description: HIFI4 core
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- description: STG AXI/AHB
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- description: USB (125 MHz)
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- description: CPU Bus
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- description: HIFI4 Axi
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- description: NOC STG Bus
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- description: APB Bus
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clock-names:
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items:
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- const: osc
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- const: hifi4_core
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- const: stg_axiahb
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- const: usb_125m
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- const: cpu_bus
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- const: hifi4_axi
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- const: nocstg_bus
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- const: apb_bus
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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'#reset-cells':
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const: 1
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description:
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See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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stgcrg: clock-controller@10230000 {
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compatible = "starfive,jh7110-stgcrg";
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reg = <0x10230000 0x10000>;
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clocks = <&osc>,
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<&syscrg JH7110_SYSCLK_HIFI4_CORE>,
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<&syscrg JH7110_SYSCLK_STG_AXIAHB>,
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<&syscrg JH7110_SYSCLK_USB_125M>,
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<&syscrg JH7110_SYSCLK_CPU_BUS>,
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<&syscrg JH7110_SYSCLK_HIFI4_AXI>,
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<&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
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<&syscrg JH7110_SYSCLK_APB_BUS>;
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clock-names = "osc", "hifi4_core",
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"stg_axiahb", "usb_125m",
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"cpu_bus", "hifi4_axi",
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"nocstg_bus", "apb_bus";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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@ -27,6 +27,9 @@ properties:
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- description: External I2S RX left/right channel clock
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- description: External TDM clock
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- description: External audio master clock
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- description: PLL0
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- description: PLL1
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- description: PLL2
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- items:
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- description: Main Oscillator (24 MHz)
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@ -38,6 +41,9 @@ properties:
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- description: External I2S RX left/right channel clock
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- description: External TDM clock
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- description: External audio master clock
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- description: PLL0
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- description: PLL1
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- description: PLL2
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clock-names:
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oneOf:
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@ -52,6 +58,9 @@ properties:
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- const: i2srx_lrck_ext
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- const: tdm_ext
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- const: mclk_ext
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- const: pll0_out
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- const: pll1_out
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- const: pll2_out
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- items:
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- const: osc
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@ -63,6 +72,9 @@ properties:
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- const: i2srx_lrck_ext
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- const: tdm_ext
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- const: mclk_ext
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- const: pll0_out
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- const: pll1_out
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- const: pll2_out
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'#clock-cells':
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const: 1
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@ -93,12 +105,14 @@ examples:
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<&gmac1_rgmii_rxin>,
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<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
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<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
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<&tdm_ext>, <&mclk_ext>;
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<&tdm_ext>, <&mclk_ext>,
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<&pllclk 0>, <&pllclk 1>, <&pllclk 2>;
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clock-names = "osc", "gmac1_rmii_refin",
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"gmac1_rgmii_rxin",
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"i2stx_bclk_ext", "i2stx_lrck_ext",
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"i2srx_bclk_ext", "i2srx_lrck_ext",
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"tdm_ext", "mclk_ext";
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"tdm_ext", "mclk_ext",
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"pll0_out", "pll1_out", "pll2_out";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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@ -0,0 +1,90 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 Video-Output Clock and Reset Generator
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maintainers:
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- Xingyu Wu <xingyu.wu@starfivetech.com>
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properties:
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compatible:
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const: starfive,jh7110-voutcrg
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Vout Top core
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- description: Vout Top Ahb
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- description: Vout Top Axi
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- description: Vout Top HDMI MCLK
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- description: I2STX0 BCLK
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- description: external HDMI pixel
|
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clock-names:
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items:
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- const: vout_src
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- const: vout_top_ahb
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- const: vout_top_axi
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- const: vout_top_hdmitx0_mclk
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- const: i2stx0_bclk
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- const: hdmitx0_pixelclk
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resets:
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maxItems: 1
|
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description: Vout Top core
|
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'#clock-cells':
|
||||
const: 1
|
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description:
|
||||
See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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'#reset-cells':
|
||||
const: 1
|
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description:
|
||||
See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
|
||||
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power-domains:
|
||||
maxItems: 1
|
||||
description:
|
||||
Vout domain power
|
||||
|
||||
required:
|
||||
- compatible
|
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- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- power-domains
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/starfive,jh7110-crg.h>
|
||||
#include <dt-bindings/power/starfive,jh7110-pmu.h>
|
||||
#include <dt-bindings/reset/starfive,jh7110-crg.h>
|
||||
|
||||
voutcrg: clock-controller@295C0000 {
|
||||
compatible = "starfive,jh7110-voutcrg";
|
||||
reg = <0x295C0000 0x10000>;
|
||||
clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
|
||||
<&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
|
||||
<&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
|
||||
<&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
|
||||
<&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
|
||||
<&hdmitx0_pixelclk>;
|
||||
clock-names = "vout_src", "vout_top_ahb",
|
||||
"vout_top_axi", "vout_top_hdmitx0_mclk",
|
||||
"i2stx0_bclk", "hdmitx0_pixelclk";
|
||||
resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
power-domains = <&pwrc JH7110_PD_VOUT>;
|
||||
};
|
||||
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@ -0,0 +1,93 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
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---
|
||||
$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
|
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$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: StarFive JH7110 SoC system controller
|
||||
|
||||
maintainers:
|
||||
- William Qiu <william.qiu@starfivetech.com>
|
||||
|
||||
description:
|
||||
The StarFive JH7110 SoC system controller provides register information such
|
||||
as offset, mask and shift to configure related modules such as MMC and PCIe.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: starfive,jh7110-sys-syscon
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
- items:
|
||||
- enum:
|
||||
- starfive,jh7110-aon-syscon
|
||||
- starfive,jh7110-stg-syscon
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clock-controller:
|
||||
$ref: /schemas/clock/starfive,jh7110-pll.yaml#
|
||||
type: object
|
||||
|
||||
"#power-domain-cells":
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: starfive,jh7110-sys-syscon
|
||||
then:
|
||||
required:
|
||||
- clock-controller
|
||||
else:
|
||||
properties:
|
||||
clock-controller: false
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: starfive,jh7110-aon-syscon
|
||||
then:
|
||||
required:
|
||||
- "#power-domain-cells"
|
||||
else:
|
||||
properties:
|
||||
"#power-domain-cells": false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
syscon@10240000 {
|
||||
compatible = "starfive,jh7110-stg-syscon", "syscon";
|
||||
reg = <0x10240000 0x1000>;
|
||||
};
|
||||
|
||||
syscon@13030000 {
|
||||
compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
|
||||
reg = <0x13030000 0x1000>;
|
||||
|
||||
clock-controller {
|
||||
compatible = "starfive,jh7110-pll";
|
||||
clocks = <&osc>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
syscon@17010000 {
|
||||
compatible = "starfive,jh7110-aon-syscon", "syscon";
|
||||
reg = <0x17010000 0x1000>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -20271,6 +20271,12 @@ S: Supported
|
|||
F: Documentation/devicetree/bindings/mmc/starfive*
|
||||
F: drivers/mmc/host/dw_mmc-starfive.c
|
||||
|
||||
STARFIVE JH7110 SYSCON
|
||||
M: William Qiu <william.qiu@starfivetech.com>
|
||||
M: Xingyu Wu <xingyu.wu@starfivetech.com>
|
||||
S: Supported
|
||||
F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
|
||||
|
||||
STARFIVE JH7110 TDM DRIVER
|
||||
M: Walker Chen <walker.chen@starfivetech.com>
|
||||
S: Maintained
|
||||
|
|
@ -20320,6 +20326,7 @@ STARFIVE SOC DRIVERS
|
|||
M: Conor Dooley <conor@kernel.org>
|
||||
S: Maintained
|
||||
T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
|
||||
F: Documentation/devicetree/bindings/soc/starfive/
|
||||
F: drivers/soc/starfive/
|
||||
|
||||
STARFIVE TRNG DRIVER
|
||||
|
|
|
|||
|
|
@ -1,11 +1,18 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
|
||||
/*
|
||||
* Copyright 2022 Emil Renner Berthing <kernel@esmil.dk>
|
||||
* Copyright 2022 StarFive Technology Co., Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
|
||||
#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
|
||||
|
||||
/* PLL clocks */
|
||||
#define JH7110_PLLCLK_PLL0_OUT 0
|
||||
#define JH7110_PLLCLK_PLL1_OUT 1
|
||||
#define JH7110_PLLCLK_PLL2_OUT 2
|
||||
#define JH7110_PLLCLK_END 3
|
||||
|
||||
/* SYSCRG clocks */
|
||||
#define JH7110_SYSCLK_CPU_ROOT 0
|
||||
#define JH7110_SYSCLK_CPU_CORE 1
|
||||
|
|
@ -218,4 +225,77 @@
|
|||
|
||||
#define JH7110_AONCLK_END 14
|
||||
|
||||
/* STGCRG clocks */
|
||||
#define JH7110_STGCLK_HIFI4_CLK_CORE 0
|
||||
#define JH7110_STGCLK_USB0_APB 1
|
||||
#define JH7110_STGCLK_USB0_UTMI_APB 2
|
||||
#define JH7110_STGCLK_USB0_AXI 3
|
||||
#define JH7110_STGCLK_USB0_LPM 4
|
||||
#define JH7110_STGCLK_USB0_STB 5
|
||||
#define JH7110_STGCLK_USB0_APP_125 6
|
||||
#define JH7110_STGCLK_USB0_REFCLK 7
|
||||
#define JH7110_STGCLK_PCIE0_AXI_MST0 8
|
||||
#define JH7110_STGCLK_PCIE0_APB 9
|
||||
#define JH7110_STGCLK_PCIE0_TL 10
|
||||
#define JH7110_STGCLK_PCIE1_AXI_MST0 11
|
||||
#define JH7110_STGCLK_PCIE1_APB 12
|
||||
#define JH7110_STGCLK_PCIE1_TL 13
|
||||
#define JH7110_STGCLK_PCIE_SLV_MAIN 14
|
||||
#define JH7110_STGCLK_SEC_AHB 15
|
||||
#define JH7110_STGCLK_SEC_MISC_AHB 16
|
||||
#define JH7110_STGCLK_GRP0_MAIN 17
|
||||
#define JH7110_STGCLK_GRP0_BUS 18
|
||||
#define JH7110_STGCLK_GRP0_STG 19
|
||||
#define JH7110_STGCLK_GRP1_MAIN 20
|
||||
#define JH7110_STGCLK_GRP1_BUS 21
|
||||
#define JH7110_STGCLK_GRP1_STG 22
|
||||
#define JH7110_STGCLK_GRP1_HIFI 23
|
||||
#define JH7110_STGCLK_E2_RTC 24
|
||||
#define JH7110_STGCLK_E2_CORE 25
|
||||
#define JH7110_STGCLK_E2_DBG 26
|
||||
#define JH7110_STGCLK_DMA1P_AXI 27
|
||||
#define JH7110_STGCLK_DMA1P_AHB 28
|
||||
|
||||
#define JH7110_STGCLK_END 29
|
||||
|
||||
/* ISPCRG clocks */
|
||||
#define JH7110_ISPCLK_DOM4_APB_FUNC 0
|
||||
#define JH7110_ISPCLK_MIPI_RX0_PXL 1
|
||||
#define JH7110_ISPCLK_DVP_INV 2
|
||||
#define JH7110_ISPCLK_M31DPHY_CFG_IN 3
|
||||
#define JH7110_ISPCLK_M31DPHY_REF_IN 4
|
||||
#define JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0 5
|
||||
#define JH7110_ISPCLK_VIN_APB 6
|
||||
#define JH7110_ISPCLK_VIN_SYS 7
|
||||
#define JH7110_ISPCLK_VIN_PIXEL_IF0 8
|
||||
#define JH7110_ISPCLK_VIN_PIXEL_IF1 9
|
||||
#define JH7110_ISPCLK_VIN_PIXEL_IF2 10
|
||||
#define JH7110_ISPCLK_VIN_PIXEL_IF3 11
|
||||
#define JH7110_ISPCLK_VIN_P_AXI_WR 12
|
||||
#define JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C 13
|
||||
|
||||
#define JH7110_ISPCLK_END 14
|
||||
|
||||
/* VOUTCRG clocks */
|
||||
#define JH7110_VOUTCLK_APB 0
|
||||
#define JH7110_VOUTCLK_DC8200_PIX 1
|
||||
#define JH7110_VOUTCLK_DSI_SYS 2
|
||||
#define JH7110_VOUTCLK_TX_ESC 3
|
||||
#define JH7110_VOUTCLK_DC8200_AXI 4
|
||||
#define JH7110_VOUTCLK_DC8200_CORE 5
|
||||
#define JH7110_VOUTCLK_DC8200_AHB 6
|
||||
#define JH7110_VOUTCLK_DC8200_PIX0 7
|
||||
#define JH7110_VOUTCLK_DC8200_PIX1 8
|
||||
#define JH7110_VOUTCLK_DOM_VOUT_TOP_LCD 9
|
||||
#define JH7110_VOUTCLK_DSITX_APB 10
|
||||
#define JH7110_VOUTCLK_DSITX_SYS 11
|
||||
#define JH7110_VOUTCLK_DSITX_DPI 12
|
||||
#define JH7110_VOUTCLK_DSITX_TXESC 13
|
||||
#define JH7110_VOUTCLK_MIPITX_DPHY_TXESC 14
|
||||
#define JH7110_VOUTCLK_HDMI_TX_MCLK 15
|
||||
#define JH7110_VOUTCLK_HDMI_TX_BCLK 16
|
||||
#define JH7110_VOUTCLK_HDMI_TX_SYS 17
|
||||
|
||||
#define JH7110_VOUTCLK_END 18
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
|
||||
/*
|
||||
* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
|
||||
* Copyright (C) 2022 StarFive Technology Co., Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__
|
||||
|
|
@ -151,4 +152,63 @@
|
|||
|
||||
#define JH7110_AONRST_END 8
|
||||
|
||||
/* STGCRG resets */
|
||||
#define JH7110_STGRST_SYSCON 0
|
||||
#define JH7110_STGRST_HIFI4_CORE 1
|
||||
#define JH7110_STGRST_HIFI4_AXI 2
|
||||
#define JH7110_STGRST_SEC_AHB 3
|
||||
#define JH7110_STGRST_E24_CORE 4
|
||||
#define JH7110_STGRST_DMA1P_AXI 5
|
||||
#define JH7110_STGRST_DMA1P_AHB 6
|
||||
#define JH7110_STGRST_USB0_AXI 7
|
||||
#define JH7110_STGRST_USB0_APB 8
|
||||
#define JH7110_STGRST_USB0_UTMI_APB 9
|
||||
#define JH7110_STGRST_USB0_PWRUP 10
|
||||
#define JH7110_STGRST_PCIE0_AXI_MST0 11
|
||||
#define JH7110_STGRST_PCIE0_AXI_SLV0 12
|
||||
#define JH7110_STGRST_PCIE0_AXI_SLV 13
|
||||
#define JH7110_STGRST_PCIE0_BRG 14
|
||||
#define JH7110_STGRST_PCIE0_CORE 15
|
||||
#define JH7110_STGRST_PCIE0_APB 16
|
||||
#define JH7110_STGRST_PCIE1_AXI_MST0 17
|
||||
#define JH7110_STGRST_PCIE1_AXI_SLV0 18
|
||||
#define JH7110_STGRST_PCIE1_AXI_SLV 19
|
||||
#define JH7110_STGRST_PCIE1_BRG 20
|
||||
#define JH7110_STGRST_PCIE1_CORE 21
|
||||
#define JH7110_STGRST_PCIE1_APB 22
|
||||
|
||||
#define JH7110_STGRST_END 23
|
||||
|
||||
/* ISPCRG resets */
|
||||
#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_P 0
|
||||
#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_C 1
|
||||
#define JH7110_ISPRST_M31DPHY_HW 2
|
||||
#define JH7110_ISPRST_M31DPHY_B09_AON 3
|
||||
#define JH7110_ISPRST_VIN_APB 4
|
||||
#define JH7110_ISPRST_VIN_PIXEL_IF0 5
|
||||
#define JH7110_ISPRST_VIN_PIXEL_IF1 6
|
||||
#define JH7110_ISPRST_VIN_PIXEL_IF2 7
|
||||
#define JH7110_ISPRST_VIN_PIXEL_IF3 8
|
||||
#define JH7110_ISPRST_VIN_SYS 9
|
||||
#define JH7110_ISPRST_VIN_P_AXI_RD 10
|
||||
#define JH7110_ISPRST_VIN_P_AXI_WR 11
|
||||
|
||||
#define JH7110_ISPRST_END 12
|
||||
|
||||
/* VOUTCRG resets */
|
||||
#define JH7110_VOUTRST_DC8200_AXI 0
|
||||
#define JH7110_VOUTRST_DC8200_AHB 1
|
||||
#define JH7110_VOUTRST_DC8200_CORE 2
|
||||
#define JH7110_VOUTRST_DSITX_DPI 3
|
||||
#define JH7110_VOUTRST_DSITX_APB 4
|
||||
#define JH7110_VOUTRST_DSITX_RXESC 5
|
||||
#define JH7110_VOUTRST_DSITX_SYS 6
|
||||
#define JH7110_VOUTRST_DSITX_TXBYTEHS 7
|
||||
#define JH7110_VOUTRST_DSITX_TXESC 8
|
||||
#define JH7110_VOUTRST_HDMI_TX_HDMI 9
|
||||
#define JH7110_VOUTRST_MIPITX_DPHY_SYS 10
|
||||
#define JH7110_VOUTRST_MIPITX_DPHY_TXBYTEHS 11
|
||||
|
||||
#define JH7110_VOUTRST_END 12
|
||||
|
||||
#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue