[ARM] mmp: enable L2 in mmp2
Enable Tauros2 L2 in mmp2. Tauros2 L2 is shared in Marvell ARM cores. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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@ -246,6 +246,8 @@ CONFIG_ARM_THUMB=y
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# CONFIG_CPU_ICACHE_DISABLE is not set
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# CONFIG_CPU_ICACHE_DISABLE is not set
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# CONFIG_CPU_DCACHE_DISABLE is not set
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# CONFIG_CPU_DCACHE_DISABLE is not set
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# CONFIG_CPU_BPREDICT_DISABLE is not set
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# CONFIG_CPU_BPREDICT_DISABLE is not set
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CONFIG_OUTER_CACHE=y
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CONFIG_CACHE_TAUROS2=y
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CONFIG_ARM_L1_CACHE_SHIFT=5
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CONFIG_ARM_L1_CACHE_SHIFT=5
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# CONFIG_ARM_ERRATA_411920 is not set
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# CONFIG_ARM_ERRATA_411920 is not set
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CONFIG_COMMON_CLKDEV=y
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CONFIG_COMMON_CLKDEV=y
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@ -15,6 +15,8 @@
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#include <linux/init.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/io.h>
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#include <asm/hardware/cache-tauros2.h>
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#include <mach/addr-map.h>
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#include <mach/addr-map.h>
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#include <mach/regs-apbc.h>
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#include <mach/regs-apbc.h>
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#include <mach/regs-apmu.h>
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#include <mach/regs-apmu.h>
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@ -99,6 +101,9 @@ static struct clk_lookup mmp2_clkregs[] = {
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static int __init mmp2_init(void)
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static int __init mmp2_init(void)
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{
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{
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if (cpu_is_mmp2()) {
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if (cpu_is_mmp2()) {
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#ifdef CONFIG_CACHE_TAUROS2
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tauros2_init();
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#endif
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mfp_init_base(MFPR_VIRT_BASE);
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mfp_init_base(MFPR_VIRT_BASE);
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mfp_init_addr(mmp2_addr_map);
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mfp_init_addr(mmp2_addr_map);
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clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs));
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clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs));
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@ -769,7 +769,7 @@ config CACHE_L2X0
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config CACHE_TAUROS2
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config CACHE_TAUROS2
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bool "Enable the Tauros2 L2 cache controller"
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bool "Enable the Tauros2 L2 cache controller"
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depends on ARCH_DOVE
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depends on (ARCH_DOVE || ARCH_MMP)
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default y
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default y
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select OUTER_CACHE
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select OUTER_CACHE
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help
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help
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