Merge branch 'perf/updates' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into devel-stable
This commit is contained in:
Russell King
commit
667832da84
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@ -21,4 +21,9 @@
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#define C(_x) PERF_COUNT_HW_CACHE_##_x
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#define CACHE_OP_UNSUPPORTED 0xFFFF
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struct pt_regs;
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extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
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extern unsigned long perf_misc_flags(struct pt_regs *regs);
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#define perf_misc_flags(regs) perf_misc_flags(regs)
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#endif /* __ARM_PERF_EVENT_H__ */
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@ -67,19 +67,19 @@ struct arm_pmu {
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cpumask_t active_irqs;
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char *name;
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irqreturn_t (*handle_irq)(int irq_num, void *dev);
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void (*enable)(struct hw_perf_event *evt, int idx);
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void (*disable)(struct hw_perf_event *evt, int idx);
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void (*enable)(struct perf_event *event);
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void (*disable)(struct perf_event *event);
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int (*get_event_idx)(struct pmu_hw_events *hw_events,
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struct hw_perf_event *hwc);
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struct perf_event *event);
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int (*set_event_filter)(struct hw_perf_event *evt,
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struct perf_event_attr *attr);
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u32 (*read_counter)(int idx);
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void (*write_counter)(int idx, u32 val);
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void (*start)(void);
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void (*stop)(void);
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u32 (*read_counter)(struct perf_event *event);
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void (*write_counter)(struct perf_event *event, u32 val);
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void (*start)(struct arm_pmu *);
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void (*stop)(struct arm_pmu *);
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void (*reset)(void *);
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int (*request_irq)(irq_handler_t handler);
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void (*free_irq)(void);
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int (*request_irq)(struct arm_pmu *, irq_handler_t handler);
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void (*free_irq)(struct arm_pmu *);
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int (*map_event)(struct perf_event *event);
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int num_events;
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atomic_t active_events;
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@ -93,15 +93,11 @@ struct arm_pmu {
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extern const struct dev_pm_ops armpmu_dev_pm_ops;
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int armpmu_register(struct arm_pmu *armpmu, char *name, int type);
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int armpmu_register(struct arm_pmu *armpmu, int type);
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u64 armpmu_event_update(struct perf_event *event,
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struct hw_perf_event *hwc,
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int idx);
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u64 armpmu_event_update(struct perf_event *event);
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int armpmu_event_set_period(struct perf_event *event,
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struct hw_perf_event *hwc,
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int idx);
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int armpmu_event_set_period(struct perf_event *event);
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int armpmu_map_event(struct perf_event *event,
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const unsigned (*event_map)[PERF_COUNT_HW_MAX],
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@ -86,12 +86,10 @@ armpmu_map_event(struct perf_event *event,
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return -ENOENT;
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}
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int
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armpmu_event_set_period(struct perf_event *event,
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struct hw_perf_event *hwc,
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int idx)
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int armpmu_event_set_period(struct perf_event *event)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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s64 left = local64_read(&hwc->period_left);
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s64 period = hwc->sample_period;
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int ret = 0;
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@ -119,24 +117,22 @@ armpmu_event_set_period(struct perf_event *event,
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local64_set(&hwc->prev_count, (u64)-left);
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armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
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armpmu->write_counter(event, (u64)(-left) & 0xffffffff);
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perf_event_update_userpage(event);
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return ret;
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}
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u64
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armpmu_event_update(struct perf_event *event,
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struct hw_perf_event *hwc,
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int idx)
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u64 armpmu_event_update(struct perf_event *event)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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u64 delta, prev_raw_count, new_raw_count;
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again:
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prev_raw_count = local64_read(&hwc->prev_count);
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new_raw_count = armpmu->read_counter(idx);
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new_raw_count = armpmu->read_counter(event);
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if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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new_raw_count) != prev_raw_count)
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@ -159,7 +155,7 @@ armpmu_read(struct perf_event *event)
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if (hwc->idx < 0)
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return;
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armpmu_event_update(event, hwc, hwc->idx);
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armpmu_event_update(event);
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}
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static void
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@ -173,14 +169,13 @@ armpmu_stop(struct perf_event *event, int flags)
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* PERF_EF_UPDATE, see comments in armpmu_start().
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*/
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if (!(hwc->state & PERF_HES_STOPPED)) {
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armpmu->disable(hwc, hwc->idx);
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armpmu_event_update(event, hwc, hwc->idx);
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armpmu->disable(event);
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armpmu_event_update(event);
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hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
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}
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}
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static void
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armpmu_start(struct perf_event *event, int flags)
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static void armpmu_start(struct perf_event *event, int flags)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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@ -200,8 +195,8 @@ armpmu_start(struct perf_event *event, int flags)
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* get an interrupt too soon or *way* too late if the overflow has
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* happened since disabling.
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*/
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armpmu_event_set_period(event, hwc, hwc->idx);
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armpmu->enable(hwc, hwc->idx);
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armpmu_event_set_period(event);
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armpmu->enable(event);
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}
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static void
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@ -233,7 +228,7 @@ armpmu_add(struct perf_event *event, int flags)
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perf_pmu_disable(event->pmu);
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/* If we don't have a space for the counter then finish early. */
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idx = armpmu->get_event_idx(hw_events, hwc);
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idx = armpmu->get_event_idx(hw_events, event);
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if (idx < 0) {
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err = idx;
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goto out;
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@ -244,7 +239,7 @@ armpmu_add(struct perf_event *event, int flags)
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* sure it is disabled.
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*/
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event->hw.idx = idx;
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armpmu->disable(hwc, idx);
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armpmu->disable(event);
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hw_events->events[idx] = event;
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hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
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@ -264,13 +259,12 @@ validate_event(struct pmu_hw_events *hw_events,
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struct perf_event *event)
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct hw_perf_event fake_event = event->hw;
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struct pmu *leader_pmu = event->group_leader->pmu;
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if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
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return 1;
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return armpmu->get_event_idx(hw_events, &fake_event) >= 0;
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return armpmu->get_event_idx(hw_events, event) >= 0;
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}
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static int
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@ -316,7 +310,7 @@ static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
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static void
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armpmu_release_hardware(struct arm_pmu *armpmu)
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{
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armpmu->free_irq();
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armpmu->free_irq(armpmu);
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pm_runtime_put_sync(&armpmu->plat_device->dev);
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}
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@ -330,7 +324,7 @@ armpmu_reserve_hardware(struct arm_pmu *armpmu)
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return -ENODEV;
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pm_runtime_get_sync(&pmu_device->dev);
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err = armpmu->request_irq(armpmu_dispatch_irq);
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err = armpmu->request_irq(armpmu, armpmu_dispatch_irq);
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if (err) {
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armpmu_release_hardware(armpmu);
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return err;
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@ -465,13 +459,13 @@ static void armpmu_enable(struct pmu *pmu)
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int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
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if (enabled)
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armpmu->start();
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armpmu->start(armpmu);
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}
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static void armpmu_disable(struct pmu *pmu)
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{
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struct arm_pmu *armpmu = to_arm_pmu(pmu);
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armpmu->stop();
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armpmu->stop(armpmu);
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}
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#ifdef CONFIG_PM_RUNTIME
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@ -517,12 +511,13 @@ static void __init armpmu_init(struct arm_pmu *armpmu)
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};
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}
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int armpmu_register(struct arm_pmu *armpmu, char *name, int type)
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int armpmu_register(struct arm_pmu *armpmu, int type)
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{
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armpmu_init(armpmu);
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pm_runtime_enable(&armpmu->plat_device->dev);
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pr_info("enabled with %s PMU driver, %d counters available\n",
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armpmu->name, armpmu->num_events);
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return perf_pmu_register(&armpmu->pmu, name, type);
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return perf_pmu_register(&armpmu->pmu, armpmu->name, type);
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}
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/*
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@ -576,6 +571,10 @@ perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
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{
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struct frame_tail __user *tail;
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if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
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/* We don't support guest os callchain now */
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return;
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}
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tail = (struct frame_tail __user *)regs->ARM_fp - 1;
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@ -603,9 +602,41 @@ perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
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{
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struct stackframe fr;
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if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
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/* We don't support guest os callchain now */
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return;
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}
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fr.fp = regs->ARM_fp;
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fr.sp = regs->ARM_sp;
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fr.lr = regs->ARM_lr;
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fr.pc = regs->ARM_pc;
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walk_stackframe(&fr, callchain_trace, entry);
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}
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unsigned long perf_instruction_pointer(struct pt_regs *regs)
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{
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if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
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return perf_guest_cbs->get_guest_ip();
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return instruction_pointer(regs);
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}
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unsigned long perf_misc_flags(struct pt_regs *regs)
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{
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int misc = 0;
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if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
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if (perf_guest_cbs->is_user_mode())
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misc |= PERF_RECORD_MISC_GUEST_USER;
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else
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misc |= PERF_RECORD_MISC_GUEST_KERNEL;
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} else {
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if (user_mode(regs))
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misc |= PERF_RECORD_MISC_USER;
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else
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misc |= PERF_RECORD_MISC_KERNEL;
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}
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return misc;
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}
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@ -23,6 +23,7 @@
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <asm/cputype.h>
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@ -45,7 +46,7 @@ const char *perf_pmu_name(void)
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if (!cpu_pmu)
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return NULL;
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return cpu_pmu->pmu.name;
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return cpu_pmu->name;
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}
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EXPORT_SYMBOL_GPL(perf_pmu_name);
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@ -70,7 +71,7 @@ static struct pmu_hw_events *cpu_pmu_get_cpu_events(void)
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return &__get_cpu_var(cpu_hw_events);
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}
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static void cpu_pmu_free_irq(void)
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static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu)
|
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{
|
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int i, irq, irqs;
|
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struct platform_device *pmu_device = cpu_pmu->plat_device;
|
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|
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@ -86,7 +87,7 @@ static void cpu_pmu_free_irq(void)
|
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}
|
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}
|
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|
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static int cpu_pmu_request_irq(irq_handler_t handler)
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static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
|
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{
|
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int i, err, irq, irqs;
|
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struct platform_device *pmu_device = cpu_pmu->plat_device;
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|
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@ -147,7 +148,7 @@ static void __devinit cpu_pmu_init(struct arm_pmu *cpu_pmu)
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|
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/* Ensure the PMU has sane values out of reset. */
|
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if (cpu_pmu && cpu_pmu->reset)
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on_each_cpu(cpu_pmu->reset, NULL, 1);
|
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on_each_cpu(cpu_pmu->reset, cpu_pmu, 1);
|
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}
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|
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/*
|
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|
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@ -163,7 +164,9 @@ static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
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return NOTIFY_DONE;
|
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|
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if (cpu_pmu && cpu_pmu->reset)
|
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cpu_pmu->reset(NULL);
|
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cpu_pmu->reset(cpu_pmu);
|
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else
|
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return NOTIFY_DONE;
|
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|
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return NOTIFY_OK;
|
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}
|
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|
|
@ -195,13 +198,13 @@ static struct platform_device_id __devinitdata cpu_pmu_plat_device_ids[] = {
|
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/*
|
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* CPU PMU identification and probing.
|
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*/
|
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static struct arm_pmu *__devinit probe_current_pmu(void)
|
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static int __devinit probe_current_pmu(struct arm_pmu *pmu)
|
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{
|
||||
struct arm_pmu *pmu = NULL;
|
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int cpu = get_cpu();
|
||||
unsigned long cpuid = read_cpuid_id();
|
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unsigned long implementor = (cpuid & 0xFF000000) >> 24;
|
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unsigned long part_number = (cpuid & 0xFFF0);
|
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int ret = -ENODEV;
|
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|
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pr_info("probing PMU on CPU %d\n", cpu);
|
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|
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|
|
@ -211,25 +214,25 @@ static struct arm_pmu *__devinit probe_current_pmu(void)
|
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case 0xB360: /* ARM1136 */
|
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case 0xB560: /* ARM1156 */
|
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case 0xB760: /* ARM1176 */
|
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pmu = armv6pmu_init();
|
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ret = armv6pmu_init(pmu);
|
||||
break;
|
||||
case 0xB020: /* ARM11mpcore */
|
||||
pmu = armv6mpcore_pmu_init();
|
||||
ret = armv6mpcore_pmu_init(pmu);
|
||||
break;
|
||||
case 0xC080: /* Cortex-A8 */
|
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pmu = armv7_a8_pmu_init();
|
||||
ret = armv7_a8_pmu_init(pmu);
|
||||
break;
|
||||
case 0xC090: /* Cortex-A9 */
|
||||
pmu = armv7_a9_pmu_init();
|
||||
ret = armv7_a9_pmu_init(pmu);
|
||||
break;
|
||||
case 0xC050: /* Cortex-A5 */
|
||||
pmu = armv7_a5_pmu_init();
|
||||
ret = armv7_a5_pmu_init(pmu);
|
||||
break;
|
||||
case 0xC0F0: /* Cortex-A15 */
|
||||
pmu = armv7_a15_pmu_init();
|
||||
ret = armv7_a15_pmu_init(pmu);
|
||||
break;
|
||||
case 0xC070: /* Cortex-A7 */
|
||||
pmu = armv7_a7_pmu_init();
|
||||
ret = armv7_a7_pmu_init(pmu);
|
||||
break;
|
||||
}
|
||||
/* Intel CPUs [xscale]. */
|
||||
|
|
@ -237,43 +240,54 @@ static struct arm_pmu *__devinit probe_current_pmu(void)
|
|||
part_number = (cpuid >> 13) & 0x7;
|
||||
switch (part_number) {
|
||||
case 1:
|
||||
pmu = xscale1pmu_init();
|
||||
ret = xscale1pmu_init(pmu);
|
||||
break;
|
||||
case 2:
|
||||
pmu = xscale2pmu_init();
|
||||
ret = xscale2pmu_init(pmu);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
put_cpu();
|
||||
return pmu;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __devinit cpu_pmu_device_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct of_device_id *of_id;
|
||||
struct arm_pmu *(*init_fn)(void);
|
||||
int (*init_fn)(struct arm_pmu *);
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
struct arm_pmu *pmu;
|
||||
int ret = -ENODEV;
|
||||
|
||||
if (cpu_pmu) {
|
||||
pr_info("attempt to register multiple PMU devices!");
|
||||
return -ENOSPC;
|
||||
}
|
||||
|
||||
if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
|
||||
init_fn = of_id->data;
|
||||
cpu_pmu = init_fn();
|
||||
} else {
|
||||
cpu_pmu = probe_current_pmu();
|
||||
pmu = kzalloc(sizeof(struct arm_pmu), GFP_KERNEL);
|
||||
if (!pmu) {
|
||||
pr_info("failed to allocate PMU device!");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
if (!cpu_pmu)
|
||||
return -ENODEV;
|
||||
if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
|
||||
init_fn = of_id->data;
|
||||
ret = init_fn(pmu);
|
||||
} else {
|
||||
ret = probe_current_pmu(pmu);
|
||||
}
|
||||
|
||||
if (ret) {
|
||||
pr_info("failed to register PMU devices!");
|
||||
kfree(pmu);
|
||||
return ret;
|
||||
}
|
||||
|
||||
cpu_pmu = pmu;
|
||||
cpu_pmu->plat_device = pdev;
|
||||
cpu_pmu_init(cpu_pmu);
|
||||
register_cpu_notifier(&cpu_pmu_hotplug_notifier);
|
||||
armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
|
||||
armpmu_register(cpu_pmu, PERF_TYPE_RAW);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -290,6 +304,16 @@ static struct platform_driver cpu_pmu_driver = {
|
|||
|
||||
static int __init register_pmu_driver(void)
|
||||
{
|
||||
return platform_driver_register(&cpu_pmu_driver);
|
||||
int err;
|
||||
|
||||
err = register_cpu_notifier(&cpu_pmu_hotplug_notifier);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = platform_driver_register(&cpu_pmu_driver);
|
||||
if (err)
|
||||
unregister_cpu_notifier(&cpu_pmu_hotplug_notifier);
|
||||
|
||||
return err;
|
||||
}
|
||||
device_initcall(register_pmu_driver);
|
||||
|
|
|
|||
|
|
@ -401,9 +401,10 @@ armv6_pmcr_counter_has_overflowed(unsigned long pmcr,
|
|||
return ret;
|
||||
}
|
||||
|
||||
static inline u32
|
||||
armv6pmu_read_counter(int counter)
|
||||
static inline u32 armv6pmu_read_counter(struct perf_event *event)
|
||||
{
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
int counter = hwc->idx;
|
||||
unsigned long value = 0;
|
||||
|
||||
if (ARMV6_CYCLE_COUNTER == counter)
|
||||
|
|
@ -418,10 +419,11 @@ armv6pmu_read_counter(int counter)
|
|||
return value;
|
||||
}
|
||||
|
||||
static inline void
|
||||
armv6pmu_write_counter(int counter,
|
||||
u32 value)
|
||||
static inline void armv6pmu_write_counter(struct perf_event *event, u32 value)
|
||||
{
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
int counter = hwc->idx;
|
||||
|
||||
if (ARMV6_CYCLE_COUNTER == counter)
|
||||
asm volatile("mcr p15, 0, %0, c15, c12, 1" : : "r"(value));
|
||||
else if (ARMV6_COUNTER0 == counter)
|
||||
|
|
@ -432,12 +434,13 @@ armv6pmu_write_counter(int counter,
|
|||
WARN_ONCE(1, "invalid counter number (%d)\n", counter);
|
||||
}
|
||||
|
||||
static void
|
||||
armv6pmu_enable_event(struct hw_perf_event *hwc,
|
||||
int idx)
|
||||
static void armv6pmu_enable_event(struct perf_event *event)
|
||||
{
|
||||
unsigned long val, mask, evt, flags;
|
||||
struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
struct pmu_hw_events *events = cpu_pmu->get_hw_events();
|
||||
int idx = hwc->idx;
|
||||
|
||||
if (ARMV6_CYCLE_COUNTER == idx) {
|
||||
mask = 0;
|
||||
|
|
@ -473,7 +476,8 @@ armv6pmu_handle_irq(int irq_num,
|
|||
{
|
||||
unsigned long pmcr = armv6_pmcr_read();
|
||||
struct perf_sample_data data;
|
||||
struct pmu_hw_events *cpuc;
|
||||
struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
|
||||
struct pmu_hw_events *cpuc = cpu_pmu->get_hw_events();
|
||||
struct pt_regs *regs;
|
||||
int idx;
|
||||
|
||||
|
|
@ -489,7 +493,6 @@ armv6pmu_handle_irq(int irq_num,
|
|||
*/
|
||||
armv6_pmcr_write(pmcr);
|
||||
|
||||
cpuc = &__get_cpu_var(cpu_hw_events);
|
||||
for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
|
||||
struct perf_event *event = cpuc->events[idx];
|
||||
struct hw_perf_event *hwc;
|
||||
|
|
@ -506,13 +509,13 @@ armv6pmu_handle_irq(int irq_num,
|
|||
continue;
|
||||
|
||||
hwc = &event->hw;
|
||||
armpmu_event_update(event, hwc, idx);
|
||||
armpmu_event_update(event);
|
||||
perf_sample_data_init(&data, 0, hwc->last_period);
|
||||
if (!armpmu_event_set_period(event, hwc, idx))
|
||||
if (!armpmu_event_set_period(event))
|
||||
continue;
|
||||
|
||||
if (perf_event_overflow(event, &data, regs))
|
||||
cpu_pmu->disable(hwc, idx);
|
||||
cpu_pmu->disable(event);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -527,8 +530,7 @@ armv6pmu_handle_irq(int irq_num,
|
|||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void
|
||||
armv6pmu_start(void)
|
||||
static void armv6pmu_start(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
unsigned long flags, val;
|
||||
struct pmu_hw_events *events = cpu_pmu->get_hw_events();
|
||||
|
|
@ -540,8 +542,7 @@ armv6pmu_start(void)
|
|||
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
|
||||
}
|
||||
|
||||
static void
|
||||
armv6pmu_stop(void)
|
||||
static void armv6pmu_stop(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
unsigned long flags, val;
|
||||
struct pmu_hw_events *events = cpu_pmu->get_hw_events();
|
||||
|
|
@ -555,10 +556,11 @@ armv6pmu_stop(void)
|
|||
|
||||
static int
|
||||
armv6pmu_get_event_idx(struct pmu_hw_events *cpuc,
|
||||
struct hw_perf_event *event)
|
||||
struct perf_event *event)
|
||||
{
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
/* Always place a cycle counter into the cycle counter. */
|
||||
if (ARMV6_PERFCTR_CPU_CYCLES == event->config_base) {
|
||||
if (ARMV6_PERFCTR_CPU_CYCLES == hwc->config_base) {
|
||||
if (test_and_set_bit(ARMV6_CYCLE_COUNTER, cpuc->used_mask))
|
||||
return -EAGAIN;
|
||||
|
||||
|
|
@ -579,12 +581,13 @@ armv6pmu_get_event_idx(struct pmu_hw_events *cpuc,
|
|||
}
|
||||
}
|
||||
|
||||
static void
|
||||
armv6pmu_disable_event(struct hw_perf_event *hwc,
|
||||
int idx)
|
||||
static void armv6pmu_disable_event(struct perf_event *event)
|
||||
{
|
||||
unsigned long val, mask, evt, flags;
|
||||
struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
struct pmu_hw_events *events = cpu_pmu->get_hw_events();
|
||||
int idx = hwc->idx;
|
||||
|
||||
if (ARMV6_CYCLE_COUNTER == idx) {
|
||||
mask = ARMV6_PMCR_CCOUNT_IEN;
|
||||
|
|
@ -613,12 +616,13 @@ armv6pmu_disable_event(struct hw_perf_event *hwc,
|
|||
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
|
||||
}
|
||||
|
||||
static void
|
||||
armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
|
||||
int idx)
|
||||
static void armv6mpcore_pmu_disable_event(struct perf_event *event)
|
||||
{
|
||||
unsigned long val, mask, flags, evt = 0;
|
||||
struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
struct pmu_hw_events *events = cpu_pmu->get_hw_events();
|
||||
int idx = hwc->idx;
|
||||
|
||||
if (ARMV6_CYCLE_COUNTER == idx) {
|
||||
mask = ARMV6_PMCR_CCOUNT_IEN;
|
||||
|
|
@ -649,24 +653,22 @@ static int armv6_map_event(struct perf_event *event)
|
|||
&armv6_perf_cache_map, 0xFF);
|
||||
}
|
||||
|
||||
static struct arm_pmu armv6pmu = {
|
||||
.name = "v6",
|
||||
.handle_irq = armv6pmu_handle_irq,
|
||||
.enable = armv6pmu_enable_event,
|
||||
.disable = armv6pmu_disable_event,
|
||||
.read_counter = armv6pmu_read_counter,
|
||||
.write_counter = armv6pmu_write_counter,
|
||||
.get_event_idx = armv6pmu_get_event_idx,
|
||||
.start = armv6pmu_start,
|
||||
.stop = armv6pmu_stop,
|
||||
.map_event = armv6_map_event,
|
||||
.num_events = 3,
|
||||
.max_period = (1LLU << 32) - 1,
|
||||
};
|
||||
|
||||
static struct arm_pmu *__devinit armv6pmu_init(void)
|
||||
static int __devinit armv6pmu_init(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
return &armv6pmu;
|
||||
cpu_pmu->name = "v6";
|
||||
cpu_pmu->handle_irq = armv6pmu_handle_irq;
|
||||
cpu_pmu->enable = armv6pmu_enable_event;
|
||||
cpu_pmu->disable = armv6pmu_disable_event;
|
||||
cpu_pmu->read_counter = armv6pmu_read_counter;
|
||||
cpu_pmu->write_counter = armv6pmu_write_counter;
|
||||
cpu_pmu->get_event_idx = armv6pmu_get_event_idx;
|
||||
cpu_pmu->start = armv6pmu_start;
|
||||
cpu_pmu->stop = armv6pmu_stop;
|
||||
cpu_pmu->map_event = armv6_map_event;
|
||||
cpu_pmu->num_events = 3;
|
||||
cpu_pmu->max_period = (1LLU << 32) - 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -683,33 +685,31 @@ static int armv6mpcore_map_event(struct perf_event *event)
|
|||
&armv6mpcore_perf_cache_map, 0xFF);
|
||||
}
|
||||
|
||||
static struct arm_pmu armv6mpcore_pmu = {
|
||||
.name = "v6mpcore",
|
||||
.handle_irq = armv6pmu_handle_irq,
|
||||
.enable = armv6pmu_enable_event,
|
||||
.disable = armv6mpcore_pmu_disable_event,
|
||||
.read_counter = armv6pmu_read_counter,
|
||||
.write_counter = armv6pmu_write_counter,
|
||||
.get_event_idx = armv6pmu_get_event_idx,
|
||||
.start = armv6pmu_start,
|
||||
.stop = armv6pmu_stop,
|
||||
.map_event = armv6mpcore_map_event,
|
||||
.num_events = 3,
|
||||
.max_period = (1LLU << 32) - 1,
|
||||
};
|
||||
|
||||
static struct arm_pmu *__devinit armv6mpcore_pmu_init(void)
|
||||
static int __devinit armv6mpcore_pmu_init(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
return &armv6mpcore_pmu;
|
||||
cpu_pmu->name = "v6mpcore";
|
||||
cpu_pmu->handle_irq = armv6pmu_handle_irq;
|
||||
cpu_pmu->enable = armv6pmu_enable_event;
|
||||
cpu_pmu->disable = armv6mpcore_pmu_disable_event;
|
||||
cpu_pmu->read_counter = armv6pmu_read_counter;
|
||||
cpu_pmu->write_counter = armv6pmu_write_counter;
|
||||
cpu_pmu->get_event_idx = armv6pmu_get_event_idx;
|
||||
cpu_pmu->start = armv6pmu_start;
|
||||
cpu_pmu->stop = armv6pmu_stop;
|
||||
cpu_pmu->map_event = armv6mpcore_map_event;
|
||||
cpu_pmu->num_events = 3;
|
||||
cpu_pmu->max_period = (1LLU << 32) - 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
static struct arm_pmu *__devinit armv6pmu_init(void)
|
||||
static int armv6pmu_init(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
return NULL;
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static struct arm_pmu *__devinit armv6mpcore_pmu_init(void)
|
||||
static int armv6mpcore_pmu_init(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
return NULL;
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif /* CONFIG_CPU_V6 || CONFIG_CPU_V6K */
|
||||
|
|
|
|||
|
|
@ -18,8 +18,6 @@
|
|||
|
||||
#ifdef CONFIG_CPU_V7
|
||||
|
||||
static struct arm_pmu armv7pmu;
|
||||
|
||||
/*
|
||||
* Common ARMv7 event types
|
||||
*
|
||||
|
|
@ -738,7 +736,8 @@ static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
|||
*/
|
||||
#define ARMV7_IDX_CYCLE_COUNTER 0
|
||||
#define ARMV7_IDX_COUNTER0 1
|
||||
#define ARMV7_IDX_COUNTER_LAST (ARMV7_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
|
||||
#define ARMV7_IDX_COUNTER_LAST(cpu_pmu) \
|
||||
(ARMV7_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
|
||||
|
||||
#define ARMV7_MAX_COUNTERS 32
|
||||
#define ARMV7_COUNTER_MASK (ARMV7_MAX_COUNTERS - 1)
|
||||
|
|
@ -804,49 +803,34 @@ static inline int armv7_pmnc_has_overflowed(u32 pmnc)
|
|||
return pmnc & ARMV7_OVERFLOWED_MASK;
|
||||
}
|
||||
|
||||
static inline int armv7_pmnc_counter_valid(int idx)
|
||||
static inline int armv7_pmnc_counter_valid(struct arm_pmu *cpu_pmu, int idx)
|
||||
{
|
||||
return idx >= ARMV7_IDX_CYCLE_COUNTER && idx <= ARMV7_IDX_COUNTER_LAST;
|
||||
return idx >= ARMV7_IDX_CYCLE_COUNTER &&
|
||||
idx <= ARMV7_IDX_COUNTER_LAST(cpu_pmu);
|
||||
}
|
||||
|
||||
static inline int armv7_pmnc_counter_has_overflowed(u32 pmnc, int idx)
|
||||
{
|
||||
int ret = 0;
|
||||
u32 counter;
|
||||
|
||||
if (!armv7_pmnc_counter_valid(idx)) {
|
||||
pr_err("CPU%u checking wrong counter %d overflow status\n",
|
||||
smp_processor_id(), idx);
|
||||
} else {
|
||||
counter = ARMV7_IDX_TO_COUNTER(idx);
|
||||
ret = pmnc & BIT(counter);
|
||||
}
|
||||
|
||||
return ret;
|
||||
return pmnc & BIT(ARMV7_IDX_TO_COUNTER(idx));
|
||||
}
|
||||
|
||||
static inline int armv7_pmnc_select_counter(int idx)
|
||||
{
|
||||
u32 counter;
|
||||
|
||||
if (!armv7_pmnc_counter_valid(idx)) {
|
||||
pr_err("CPU%u selecting wrong PMNC counter %d\n",
|
||||
smp_processor_id(), idx);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
counter = ARMV7_IDX_TO_COUNTER(idx);
|
||||
u32 counter = ARMV7_IDX_TO_COUNTER(idx);
|
||||
asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (counter));
|
||||
isb();
|
||||
|
||||
return idx;
|
||||
}
|
||||
|
||||
static inline u32 armv7pmu_read_counter(int idx)
|
||||
static inline u32 armv7pmu_read_counter(struct perf_event *event)
|
||||
{
|
||||
struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
int idx = hwc->idx;
|
||||
u32 value = 0;
|
||||
|
||||
if (!armv7_pmnc_counter_valid(idx))
|
||||
if (!armv7_pmnc_counter_valid(cpu_pmu, idx))
|
||||
pr_err("CPU%u reading wrong counter %d\n",
|
||||
smp_processor_id(), idx);
|
||||
else if (idx == ARMV7_IDX_CYCLE_COUNTER)
|
||||
|
|
@ -857,9 +841,13 @@ static inline u32 armv7pmu_read_counter(int idx)
|
|||
return value;
|
||||
}
|
||||
|
||||
static inline void armv7pmu_write_counter(int idx, u32 value)
|
||||
static inline void armv7pmu_write_counter(struct perf_event *event, u32 value)
|
||||
{
|
||||
if (!armv7_pmnc_counter_valid(idx))
|
||||
struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
int idx = hwc->idx;
|
||||
|
||||
if (!armv7_pmnc_counter_valid(cpu_pmu, idx))
|
||||
pr_err("CPU%u writing wrong counter %d\n",
|
||||
smp_processor_id(), idx);
|
||||
else if (idx == ARMV7_IDX_CYCLE_COUNTER)
|
||||
|
|
@ -878,60 +866,28 @@ static inline void armv7_pmnc_write_evtsel(int idx, u32 val)
|
|||
|
||||
static inline int armv7_pmnc_enable_counter(int idx)
|
||||
{
|
||||
u32 counter;
|
||||
|
||||
if (!armv7_pmnc_counter_valid(idx)) {
|
||||
pr_err("CPU%u enabling wrong PMNC counter %d\n",
|
||||
smp_processor_id(), idx);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
counter = ARMV7_IDX_TO_COUNTER(idx);
|
||||
u32 counter = ARMV7_IDX_TO_COUNTER(idx);
|
||||
asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (BIT(counter)));
|
||||
return idx;
|
||||
}
|
||||
|
||||
static inline int armv7_pmnc_disable_counter(int idx)
|
||||
{
|
||||
u32 counter;
|
||||
|
||||
if (!armv7_pmnc_counter_valid(idx)) {
|
||||
pr_err("CPU%u disabling wrong PMNC counter %d\n",
|
||||
smp_processor_id(), idx);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
counter = ARMV7_IDX_TO_COUNTER(idx);
|
||||
u32 counter = ARMV7_IDX_TO_COUNTER(idx);
|
||||
asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (BIT(counter)));
|
||||
return idx;
|
||||
}
|
||||
|
||||
static inline int armv7_pmnc_enable_intens(int idx)
|
||||
{
|
||||
u32 counter;
|
||||
|
||||
if (!armv7_pmnc_counter_valid(idx)) {
|
||||
pr_err("CPU%u enabling wrong PMNC counter IRQ enable %d\n",
|
||||
smp_processor_id(), idx);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
counter = ARMV7_IDX_TO_COUNTER(idx);
|
||||
u32 counter = ARMV7_IDX_TO_COUNTER(idx);
|
||||
asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (BIT(counter)));
|
||||
return idx;
|
||||
}
|
||||
|
||||
static inline int armv7_pmnc_disable_intens(int idx)
|
||||
{
|
||||
u32 counter;
|
||||
|
||||
if (!armv7_pmnc_counter_valid(idx)) {
|
||||
pr_err("CPU%u disabling wrong PMNC counter IRQ enable %d\n",
|
||||
smp_processor_id(), idx);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
counter = ARMV7_IDX_TO_COUNTER(idx);
|
||||
u32 counter = ARMV7_IDX_TO_COUNTER(idx);
|
||||
asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(counter)));
|
||||
isb();
|
||||
/* Clear the overflow flag in case an interrupt is pending. */
|
||||
|
|
@ -956,7 +912,7 @@ static inline u32 armv7_pmnc_getreset_flags(void)
|
|||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
static void armv7_pmnc_dump_regs(void)
|
||||
static void armv7_pmnc_dump_regs(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
u32 val;
|
||||
unsigned int cnt;
|
||||
|
|
@ -981,7 +937,8 @@ static void armv7_pmnc_dump_regs(void)
|
|||
asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
|
||||
printk(KERN_INFO "CCNT =0x%08x\n", val);
|
||||
|
||||
for (cnt = ARMV7_IDX_COUNTER0; cnt <= ARMV7_IDX_COUNTER_LAST; cnt++) {
|
||||
for (cnt = ARMV7_IDX_COUNTER0;
|
||||
cnt <= ARMV7_IDX_COUNTER_LAST(cpu_pmu); cnt++) {
|
||||
armv7_pmnc_select_counter(cnt);
|
||||
asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
|
||||
printk(KERN_INFO "CNT[%d] count =0x%08x\n",
|
||||
|
|
@ -993,10 +950,19 @@ static void armv7_pmnc_dump_regs(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
static void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
|
||||
static void armv7pmu_enable_event(struct perf_event *event)
|
||||
{
|
||||
unsigned long flags;
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
|
||||
struct pmu_hw_events *events = cpu_pmu->get_hw_events();
|
||||
int idx = hwc->idx;
|
||||
|
||||
if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) {
|
||||
pr_err("CPU%u enabling wrong PMNC counter IRQ enable %d\n",
|
||||
smp_processor_id(), idx);
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable counter and interrupt, and set the counter to count
|
||||
|
|
@ -1014,7 +980,7 @@ static void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
|
|||
* We only need to set the event for the cycle counter if we
|
||||
* have the ability to perform event filtering.
|
||||
*/
|
||||
if (armv7pmu.set_event_filter || idx != ARMV7_IDX_CYCLE_COUNTER)
|
||||
if (cpu_pmu->set_event_filter || idx != ARMV7_IDX_CYCLE_COUNTER)
|
||||
armv7_pmnc_write_evtsel(idx, hwc->config_base);
|
||||
|
||||
/*
|
||||
|
|
@ -1030,10 +996,19 @@ static void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
|
|||
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
|
||||
}
|
||||
|
||||
static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx)
|
||||
static void armv7pmu_disable_event(struct perf_event *event)
|
||||
{
|
||||
unsigned long flags;
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
|
||||
struct pmu_hw_events *events = cpu_pmu->get_hw_events();
|
||||
int idx = hwc->idx;
|
||||
|
||||
if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) {
|
||||
pr_err("CPU%u disabling wrong PMNC counter IRQ enable %d\n",
|
||||
smp_processor_id(), idx);
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Disable counter and interrupt
|
||||
|
|
@ -1057,7 +1032,8 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
|
|||
{
|
||||
u32 pmnc;
|
||||
struct perf_sample_data data;
|
||||
struct pmu_hw_events *cpuc;
|
||||
struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
|
||||
struct pmu_hw_events *cpuc = cpu_pmu->get_hw_events();
|
||||
struct pt_regs *regs;
|
||||
int idx;
|
||||
|
||||
|
|
@ -1077,7 +1053,6 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
|
|||
*/
|
||||
regs = get_irq_regs();
|
||||
|
||||
cpuc = &__get_cpu_var(cpu_hw_events);
|
||||
for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
|
||||
struct perf_event *event = cpuc->events[idx];
|
||||
struct hw_perf_event *hwc;
|
||||
|
|
@ -1094,13 +1069,13 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
|
|||
continue;
|
||||
|
||||
hwc = &event->hw;
|
||||
armpmu_event_update(event, hwc, idx);
|
||||
armpmu_event_update(event);
|
||||
perf_sample_data_init(&data, 0, hwc->last_period);
|
||||
if (!armpmu_event_set_period(event, hwc, idx))
|
||||
if (!armpmu_event_set_period(event))
|
||||
continue;
|
||||
|
||||
if (perf_event_overflow(event, &data, regs))
|
||||
cpu_pmu->disable(hwc, idx);
|
||||
cpu_pmu->disable(event);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -1115,7 +1090,7 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
|
|||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void armv7pmu_start(void)
|
||||
static void armv7pmu_start(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
unsigned long flags;
|
||||
struct pmu_hw_events *events = cpu_pmu->get_hw_events();
|
||||
|
|
@ -1126,7 +1101,7 @@ static void armv7pmu_start(void)
|
|||
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
|
||||
}
|
||||
|
||||
static void armv7pmu_stop(void)
|
||||
static void armv7pmu_stop(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
unsigned long flags;
|
||||
struct pmu_hw_events *events = cpu_pmu->get_hw_events();
|
||||
|
|
@ -1138,10 +1113,12 @@ static void armv7pmu_stop(void)
|
|||
}
|
||||
|
||||
static int armv7pmu_get_event_idx(struct pmu_hw_events *cpuc,
|
||||
struct hw_perf_event *event)
|
||||
struct perf_event *event)
|
||||
{
|
||||
int idx;
|
||||
unsigned long evtype = event->config_base & ARMV7_EVTYPE_EVENT;
|
||||
struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
unsigned long evtype = hwc->config_base & ARMV7_EVTYPE_EVENT;
|
||||
|
||||
/* Always place a cycle counter into the cycle counter. */
|
||||
if (evtype == ARMV7_PERFCTR_CPU_CYCLES) {
|
||||
|
|
@ -1192,11 +1169,14 @@ static int armv7pmu_set_event_filter(struct hw_perf_event *event,
|
|||
|
||||
static void armv7pmu_reset(void *info)
|
||||
{
|
||||
struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
|
||||
u32 idx, nb_cnt = cpu_pmu->num_events;
|
||||
|
||||
/* The counter and interrupt enable registers are unknown at reset. */
|
||||
for (idx = ARMV7_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx)
|
||||
armv7pmu_disable_event(NULL, idx);
|
||||
for (idx = ARMV7_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) {
|
||||
armv7_pmnc_disable_counter(idx);
|
||||
armv7_pmnc_disable_intens(idx);
|
||||
}
|
||||
|
||||
/* Initialize & Reset PMNC: C and P bits */
|
||||
armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C);
|
||||
|
|
@ -1232,17 +1212,18 @@ static int armv7_a7_map_event(struct perf_event *event)
|
|||
&armv7_a7_perf_cache_map, 0xFF);
|
||||
}
|
||||
|
||||
static struct arm_pmu armv7pmu = {
|
||||
.handle_irq = armv7pmu_handle_irq,
|
||||
.enable = armv7pmu_enable_event,
|
||||
.disable = armv7pmu_disable_event,
|
||||
.read_counter = armv7pmu_read_counter,
|
||||
.write_counter = armv7pmu_write_counter,
|
||||
.get_event_idx = armv7pmu_get_event_idx,
|
||||
.start = armv7pmu_start,
|
||||
.stop = armv7pmu_stop,
|
||||
.reset = armv7pmu_reset,
|
||||
.max_period = (1LLU << 32) - 1,
|
||||
static void armv7pmu_init(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
cpu_pmu->handle_irq = armv7pmu_handle_irq;
|
||||
cpu_pmu->enable = armv7pmu_enable_event;
|
||||
cpu_pmu->disable = armv7pmu_disable_event;
|
||||
cpu_pmu->read_counter = armv7pmu_read_counter;
|
||||
cpu_pmu->write_counter = armv7pmu_write_counter;
|
||||
cpu_pmu->get_event_idx = armv7pmu_get_event_idx;
|
||||
cpu_pmu->start = armv7pmu_start;
|
||||
cpu_pmu->stop = armv7pmu_stop;
|
||||
cpu_pmu->reset = armv7pmu_reset;
|
||||
cpu_pmu->max_period = (1LLU << 32) - 1;
|
||||
};
|
||||
|
||||
static u32 __devinit armv7_read_num_pmnc_events(void)
|
||||
|
|
@ -1256,70 +1237,75 @@ static u32 __devinit armv7_read_num_pmnc_events(void)
|
|||
return nb_cnt + 1;
|
||||
}
|
||||
|
||||
static struct arm_pmu *__devinit armv7_a8_pmu_init(void)
|
||||
static int __devinit armv7_a8_pmu_init(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
armv7pmu.name = "ARMv7 Cortex-A8";
|
||||
armv7pmu.map_event = armv7_a8_map_event;
|
||||
armv7pmu.num_events = armv7_read_num_pmnc_events();
|
||||
return &armv7pmu;
|
||||
armv7pmu_init(cpu_pmu);
|
||||
cpu_pmu->name = "ARMv7 Cortex-A8";
|
||||
cpu_pmu->map_event = armv7_a8_map_event;
|
||||
cpu_pmu->num_events = armv7_read_num_pmnc_events();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct arm_pmu *__devinit armv7_a9_pmu_init(void)
|
||||
static int __devinit armv7_a9_pmu_init(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
armv7pmu.name = "ARMv7 Cortex-A9";
|
||||
armv7pmu.map_event = armv7_a9_map_event;
|
||||
armv7pmu.num_events = armv7_read_num_pmnc_events();
|
||||
return &armv7pmu;
|
||||
armv7pmu_init(cpu_pmu);
|
||||
cpu_pmu->name = "ARMv7 Cortex-A9";
|
||||
cpu_pmu->map_event = armv7_a9_map_event;
|
||||
cpu_pmu->num_events = armv7_read_num_pmnc_events();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct arm_pmu *__devinit armv7_a5_pmu_init(void)
|
||||
static int __devinit armv7_a5_pmu_init(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
armv7pmu.name = "ARMv7 Cortex-A5";
|
||||
armv7pmu.map_event = armv7_a5_map_event;
|
||||
armv7pmu.num_events = armv7_read_num_pmnc_events();
|
||||
return &armv7pmu;
|
||||
armv7pmu_init(cpu_pmu);
|
||||
cpu_pmu->name = "ARMv7 Cortex-A5";
|
||||
cpu_pmu->map_event = armv7_a5_map_event;
|
||||
cpu_pmu->num_events = armv7_read_num_pmnc_events();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct arm_pmu *__devinit armv7_a15_pmu_init(void)
|
||||
static int __devinit armv7_a15_pmu_init(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
armv7pmu.name = "ARMv7 Cortex-A15";
|
||||
armv7pmu.map_event = armv7_a15_map_event;
|
||||
armv7pmu.num_events = armv7_read_num_pmnc_events();
|
||||
armv7pmu.set_event_filter = armv7pmu_set_event_filter;
|
||||
return &armv7pmu;
|
||||
armv7pmu_init(cpu_pmu);
|
||||
cpu_pmu->name = "ARMv7 Cortex-A15";
|
||||
cpu_pmu->map_event = armv7_a15_map_event;
|
||||
cpu_pmu->num_events = armv7_read_num_pmnc_events();
|
||||
cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct arm_pmu *__devinit armv7_a7_pmu_init(void)
|
||||
static int __devinit armv7_a7_pmu_init(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
armv7pmu.name = "ARMv7 Cortex-A7";
|
||||
armv7pmu.map_event = armv7_a7_map_event;
|
||||
armv7pmu.num_events = armv7_read_num_pmnc_events();
|
||||
armv7pmu.set_event_filter = armv7pmu_set_event_filter;
|
||||
return &armv7pmu;
|
||||
armv7pmu_init(cpu_pmu);
|
||||
cpu_pmu->name = "ARMv7 Cortex-A7";
|
||||
cpu_pmu->map_event = armv7_a7_map_event;
|
||||
cpu_pmu->num_events = armv7_read_num_pmnc_events();
|
||||
cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
static struct arm_pmu *__devinit armv7_a8_pmu_init(void)
|
||||
static inline int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
return NULL;
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static struct arm_pmu *__devinit armv7_a9_pmu_init(void)
|
||||
static inline int armv7_a9_pmu_init(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
return NULL;
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static struct arm_pmu *__devinit armv7_a5_pmu_init(void)
|
||||
static inline int armv7_a5_pmu_init(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
return NULL;
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static struct arm_pmu *__devinit armv7_a15_pmu_init(void)
|
||||
static inline int armv7_a15_pmu_init(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
return NULL;
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static struct arm_pmu *__devinit armv7_a7_pmu_init(void)
|
||||
static inline int armv7_a7_pmu_init(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
return NULL;
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif /* CONFIG_CPU_V7 */
|
||||
|
|
|
|||
|
|
@ -224,7 +224,8 @@ xscale1pmu_handle_irq(int irq_num, void *dev)
|
|||
{
|
||||
unsigned long pmnc;
|
||||
struct perf_sample_data data;
|
||||
struct pmu_hw_events *cpuc;
|
||||
struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
|
||||
struct pmu_hw_events *cpuc = cpu_pmu->get_hw_events();
|
||||
struct pt_regs *regs;
|
||||
int idx;
|
||||
|
||||
|
|
@ -248,7 +249,6 @@ xscale1pmu_handle_irq(int irq_num, void *dev)
|
|||
|
||||
regs = get_irq_regs();
|
||||
|
||||
cpuc = &__get_cpu_var(cpu_hw_events);
|
||||
for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
|
||||
struct perf_event *event = cpuc->events[idx];
|
||||
struct hw_perf_event *hwc;
|
||||
|
|
@ -260,13 +260,13 @@ xscale1pmu_handle_irq(int irq_num, void *dev)
|
|||
continue;
|
||||
|
||||
hwc = &event->hw;
|
||||
armpmu_event_update(event, hwc, idx);
|
||||
armpmu_event_update(event);
|
||||
perf_sample_data_init(&data, 0, hwc->last_period);
|
||||
if (!armpmu_event_set_period(event, hwc, idx))
|
||||
if (!armpmu_event_set_period(event))
|
||||
continue;
|
||||
|
||||
if (perf_event_overflow(event, &data, regs))
|
||||
cpu_pmu->disable(hwc, idx);
|
||||
cpu_pmu->disable(event);
|
||||
}
|
||||
|
||||
irq_work_run();
|
||||
|
|
@ -280,11 +280,13 @@ xscale1pmu_handle_irq(int irq_num, void *dev)
|
|||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void
|
||||
xscale1pmu_enable_event(struct hw_perf_event *hwc, int idx)
|
||||
static void xscale1pmu_enable_event(struct perf_event *event)
|
||||
{
|
||||
unsigned long val, mask, evt, flags;
|
||||
struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
struct pmu_hw_events *events = cpu_pmu->get_hw_events();
|
||||
int idx = hwc->idx;
|
||||
|
||||
switch (idx) {
|
||||
case XSCALE_CYCLE_COUNTER:
|
||||
|
|
@ -314,11 +316,13 @@ xscale1pmu_enable_event(struct hw_perf_event *hwc, int idx)
|
|||
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
|
||||
}
|
||||
|
||||
static void
|
||||
xscale1pmu_disable_event(struct hw_perf_event *hwc, int idx)
|
||||
static void xscale1pmu_disable_event(struct perf_event *event)
|
||||
{
|
||||
unsigned long val, mask, evt, flags;
|
||||
struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
struct pmu_hw_events *events = cpu_pmu->get_hw_events();
|
||||
int idx = hwc->idx;
|
||||
|
||||
switch (idx) {
|
||||
case XSCALE_CYCLE_COUNTER:
|
||||
|
|
@ -348,9 +352,10 @@ xscale1pmu_disable_event(struct hw_perf_event *hwc, int idx)
|
|||
|
||||
static int
|
||||
xscale1pmu_get_event_idx(struct pmu_hw_events *cpuc,
|
||||
struct hw_perf_event *event)
|
||||
struct perf_event *event)
|
||||
{
|
||||
if (XSCALE_PERFCTR_CCNT == event->config_base) {
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
if (XSCALE_PERFCTR_CCNT == hwc->config_base) {
|
||||
if (test_and_set_bit(XSCALE_CYCLE_COUNTER, cpuc->used_mask))
|
||||
return -EAGAIN;
|
||||
|
||||
|
|
@ -366,8 +371,7 @@ xscale1pmu_get_event_idx(struct pmu_hw_events *cpuc,
|
|||
}
|
||||
}
|
||||
|
||||
static void
|
||||
xscale1pmu_start(void)
|
||||
static void xscale1pmu_start(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
unsigned long flags, val;
|
||||
struct pmu_hw_events *events = cpu_pmu->get_hw_events();
|
||||
|
|
@ -379,8 +383,7 @@ xscale1pmu_start(void)
|
|||
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
|
||||
}
|
||||
|
||||
static void
|
||||
xscale1pmu_stop(void)
|
||||
static void xscale1pmu_stop(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
unsigned long flags, val;
|
||||
struct pmu_hw_events *events = cpu_pmu->get_hw_events();
|
||||
|
|
@ -392,9 +395,10 @@ xscale1pmu_stop(void)
|
|||
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
|
||||
}
|
||||
|
||||
static inline u32
|
||||
xscale1pmu_read_counter(int counter)
|
||||
static inline u32 xscale1pmu_read_counter(struct perf_event *event)
|
||||
{
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
int counter = hwc->idx;
|
||||
u32 val = 0;
|
||||
|
||||
switch (counter) {
|
||||
|
|
@ -412,9 +416,11 @@ xscale1pmu_read_counter(int counter)
|
|||
return val;
|
||||
}
|
||||
|
||||
static inline void
|
||||
xscale1pmu_write_counter(int counter, u32 val)
|
||||
static inline void xscale1pmu_write_counter(struct perf_event *event, u32 val)
|
||||
{
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
int counter = hwc->idx;
|
||||
|
||||
switch (counter) {
|
||||
case XSCALE_CYCLE_COUNTER:
|
||||
asm volatile("mcr p14, 0, %0, c1, c0, 0" : : "r" (val));
|
||||
|
|
@ -434,24 +440,22 @@ static int xscale_map_event(struct perf_event *event)
|
|||
&xscale_perf_cache_map, 0xFF);
|
||||
}
|
||||
|
||||
static struct arm_pmu xscale1pmu = {
|
||||
.name = "xscale1",
|
||||
.handle_irq = xscale1pmu_handle_irq,
|
||||
.enable = xscale1pmu_enable_event,
|
||||
.disable = xscale1pmu_disable_event,
|
||||
.read_counter = xscale1pmu_read_counter,
|
||||
.write_counter = xscale1pmu_write_counter,
|
||||
.get_event_idx = xscale1pmu_get_event_idx,
|
||||
.start = xscale1pmu_start,
|
||||
.stop = xscale1pmu_stop,
|
||||
.map_event = xscale_map_event,
|
||||
.num_events = 3,
|
||||
.max_period = (1LLU << 32) - 1,
|
||||
};
|
||||
|
||||
static struct arm_pmu *__devinit xscale1pmu_init(void)
|
||||
static int __devinit xscale1pmu_init(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
return &xscale1pmu;
|
||||
cpu_pmu->name = "xscale1";
|
||||
cpu_pmu->handle_irq = xscale1pmu_handle_irq;
|
||||
cpu_pmu->enable = xscale1pmu_enable_event;
|
||||
cpu_pmu->disable = xscale1pmu_disable_event;
|
||||
cpu_pmu->read_counter = xscale1pmu_read_counter;
|
||||
cpu_pmu->write_counter = xscale1pmu_write_counter;
|
||||
cpu_pmu->get_event_idx = xscale1pmu_get_event_idx;
|
||||
cpu_pmu->start = xscale1pmu_start;
|
||||
cpu_pmu->stop = xscale1pmu_stop;
|
||||
cpu_pmu->map_event = xscale_map_event;
|
||||
cpu_pmu->num_events = 3;
|
||||
cpu_pmu->max_period = (1LLU << 32) - 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define XSCALE2_OVERFLOWED_MASK 0x01f
|
||||
|
|
@ -567,7 +571,8 @@ xscale2pmu_handle_irq(int irq_num, void *dev)
|
|||
{
|
||||
unsigned long pmnc, of_flags;
|
||||
struct perf_sample_data data;
|
||||
struct pmu_hw_events *cpuc;
|
||||
struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
|
||||
struct pmu_hw_events *cpuc = cpu_pmu->get_hw_events();
|
||||
struct pt_regs *regs;
|
||||
int idx;
|
||||
|
||||
|
|
@ -585,7 +590,6 @@ xscale2pmu_handle_irq(int irq_num, void *dev)
|
|||
|
||||
regs = get_irq_regs();
|
||||
|
||||
cpuc = &__get_cpu_var(cpu_hw_events);
|
||||
for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
|
||||
struct perf_event *event = cpuc->events[idx];
|
||||
struct hw_perf_event *hwc;
|
||||
|
|
@ -597,13 +601,13 @@ xscale2pmu_handle_irq(int irq_num, void *dev)
|
|||
continue;
|
||||
|
||||
hwc = &event->hw;
|
||||
armpmu_event_update(event, hwc, idx);
|
||||
armpmu_event_update(event);
|
||||
perf_sample_data_init(&data, 0, hwc->last_period);
|
||||
if (!armpmu_event_set_period(event, hwc, idx))
|
||||
if (!armpmu_event_set_period(event))
|
||||
continue;
|
||||
|
||||
if (perf_event_overflow(event, &data, regs))
|
||||
cpu_pmu->disable(hwc, idx);
|
||||
cpu_pmu->disable(event);
|
||||
}
|
||||
|
||||
irq_work_run();
|
||||
|
|
@ -617,11 +621,13 @@ xscale2pmu_handle_irq(int irq_num, void *dev)
|
|||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void
|
||||
xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx)
|
||||
static void xscale2pmu_enable_event(struct perf_event *event)
|
||||
{
|
||||
unsigned long flags, ien, evtsel;
|
||||
struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
struct pmu_hw_events *events = cpu_pmu->get_hw_events();
|
||||
int idx = hwc->idx;
|
||||
|
||||
ien = xscale2pmu_read_int_enable();
|
||||
evtsel = xscale2pmu_read_event_select();
|
||||
|
|
@ -661,11 +667,13 @@ xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx)
|
|||
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
|
||||
}
|
||||
|
||||
static void
|
||||
xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
|
||||
static void xscale2pmu_disable_event(struct perf_event *event)
|
||||
{
|
||||
unsigned long flags, ien, evtsel, of_flags;
|
||||
struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
struct pmu_hw_events *events = cpu_pmu->get_hw_events();
|
||||
int idx = hwc->idx;
|
||||
|
||||
ien = xscale2pmu_read_int_enable();
|
||||
evtsel = xscale2pmu_read_event_select();
|
||||
|
|
@ -713,7 +721,7 @@ xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
|
|||
|
||||
static int
|
||||
xscale2pmu_get_event_idx(struct pmu_hw_events *cpuc,
|
||||
struct hw_perf_event *event)
|
||||
struct perf_event *event)
|
||||
{
|
||||
int idx = xscale1pmu_get_event_idx(cpuc, event);
|
||||
if (idx >= 0)
|
||||
|
|
@ -727,8 +735,7 @@ out:
|
|||
return idx;
|
||||
}
|
||||
|
||||
static void
|
||||
xscale2pmu_start(void)
|
||||
static void xscale2pmu_start(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
unsigned long flags, val;
|
||||
struct pmu_hw_events *events = cpu_pmu->get_hw_events();
|
||||
|
|
@ -740,8 +747,7 @@ xscale2pmu_start(void)
|
|||
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
|
||||
}
|
||||
|
||||
static void
|
||||
xscale2pmu_stop(void)
|
||||
static void xscale2pmu_stop(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
unsigned long flags, val;
|
||||
struct pmu_hw_events *events = cpu_pmu->get_hw_events();
|
||||
|
|
@ -753,9 +759,10 @@ xscale2pmu_stop(void)
|
|||
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
|
||||
}
|
||||
|
||||
static inline u32
|
||||
xscale2pmu_read_counter(int counter)
|
||||
static inline u32 xscale2pmu_read_counter(struct perf_event *event)
|
||||
{
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
int counter = hwc->idx;
|
||||
u32 val = 0;
|
||||
|
||||
switch (counter) {
|
||||
|
|
@ -779,9 +786,11 @@ xscale2pmu_read_counter(int counter)
|
|||
return val;
|
||||
}
|
||||
|
||||
static inline void
|
||||
xscale2pmu_write_counter(int counter, u32 val)
|
||||
static inline void xscale2pmu_write_counter(struct perf_event *event, u32 val)
|
||||
{
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
int counter = hwc->idx;
|
||||
|
||||
switch (counter) {
|
||||
case XSCALE_CYCLE_COUNTER:
|
||||
asm volatile("mcr p14, 0, %0, c1, c1, 0" : : "r" (val));
|
||||
|
|
@ -801,33 +810,31 @@ xscale2pmu_write_counter(int counter, u32 val)
|
|||
}
|
||||
}
|
||||
|
||||
static struct arm_pmu xscale2pmu = {
|
||||
.name = "xscale2",
|
||||
.handle_irq = xscale2pmu_handle_irq,
|
||||
.enable = xscale2pmu_enable_event,
|
||||
.disable = xscale2pmu_disable_event,
|
||||
.read_counter = xscale2pmu_read_counter,
|
||||
.write_counter = xscale2pmu_write_counter,
|
||||
.get_event_idx = xscale2pmu_get_event_idx,
|
||||
.start = xscale2pmu_start,
|
||||
.stop = xscale2pmu_stop,
|
||||
.map_event = xscale_map_event,
|
||||
.num_events = 5,
|
||||
.max_period = (1LLU << 32) - 1,
|
||||
};
|
||||
|
||||
static struct arm_pmu *__devinit xscale2pmu_init(void)
|
||||
static int __devinit xscale2pmu_init(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
return &xscale2pmu;
|
||||
cpu_pmu->name = "xscale2";
|
||||
cpu_pmu->handle_irq = xscale2pmu_handle_irq;
|
||||
cpu_pmu->enable = xscale2pmu_enable_event;
|
||||
cpu_pmu->disable = xscale2pmu_disable_event;
|
||||
cpu_pmu->read_counter = xscale2pmu_read_counter;
|
||||
cpu_pmu->write_counter = xscale2pmu_write_counter;
|
||||
cpu_pmu->get_event_idx = xscale2pmu_get_event_idx;
|
||||
cpu_pmu->start = xscale2pmu_start;
|
||||
cpu_pmu->stop = xscale2pmu_stop;
|
||||
cpu_pmu->map_event = xscale_map_event;
|
||||
cpu_pmu->num_events = 5;
|
||||
cpu_pmu->max_period = (1LLU << 32) - 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
static struct arm_pmu *__devinit xscale1pmu_init(void)
|
||||
static inline int xscale1pmu_init(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
return NULL;
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static struct arm_pmu *__devinit xscale2pmu_init(void)
|
||||
static inline int xscale2pmu_init(struct arm_pmu *cpu_pmu)
|
||||
{
|
||||
return NULL;
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif /* CONFIG_CPU_XSCALE */
|
||||
|
|
|
|||
|
|
@ -57,8 +57,6 @@ static int __init omap2_init_pmu(unsigned oh_num, char *oh_names[])
|
|||
if (IS_ERR(omap_pmu_dev))
|
||||
return PTR_ERR(omap_pmu_dev);
|
||||
|
||||
pm_runtime_enable(&omap_pmu_dev->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue