drm/amd/display: Add DCN3 GPIO
Add support to program GPIO HW block Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
21f4809ae4
commit
666ed8bfd1
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@ -87,6 +87,16 @@ AMD_DAL_GPIO_DCN21 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn21/,$(GPIO_DCN21))
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AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN21)
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endif
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###############################################################################
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# DCN 3
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###############################################################################
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ifdef CONFIG_DRM_AMD_DC_DCN3_0
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GPIO_DCN30 = hw_translate_dcn30.o hw_factory_dcn30.o
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AMD_DAL_GPIO_DCN30 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn30/,$(GPIO_DCN30))
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AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN30)
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endif
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###############################################################################
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# Diagnostics on FPGA
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###############################################################################
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GPIO_DIAG_FPGA = hw_translate_diag.o hw_factory_diag.o
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@ -0,0 +1,257 @@
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/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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#include "dm_services.h"
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#include "include/gpio_types.h"
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#include "../hw_factory.h"
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#include "../hw_gpio.h"
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#include "../hw_ddc.h"
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#include "../hw_hpd.h"
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#include "../hw_generic.h"
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#include "hw_factory_dcn30.h"
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#include "sienna_cichlid_ip_offset.h"
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#include "dcn/dcn_3_0_0_offset.h"
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#include "dcn/dcn_3_0_0_sh_mask.h"
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#include "nbio/nbio_7_4_offset.h"
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#include "dcn/dpcs_3_0_0_offset.h"
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#include "dcn/dpcs_3_0_0_sh_mask.h"
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#include "mmhub/mmhub_2_0_0_offset.h"
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#include "mmhub/mmhub_2_0_0_sh_mask.h"
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#include "reg_helper.h"
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#include "../hpd_regs.h"
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/* begin *********************
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* macros to expend register list macro defined in HW object header file */
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/* DCN */
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#define block HPD
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#define reg_num 0
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#undef BASE_INNER
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#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
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#define BASE(seg) BASE_INNER(seg)
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#define REG(reg_name)\
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BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
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#define SF_HPD(reg_name, field_name, post_fix)\
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.field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
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#define REGI(reg_name, block, id)\
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BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
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mm ## block ## id ## _ ## reg_name
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#define SF(reg_name, field_name, post_fix)\
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.field_name = reg_name ## __ ## field_name ## post_fix
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/* macros to expend register list macro defined in HW object header file
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* end *********************/
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#define hpd_regs(id) \
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{\
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HPD_REG_LIST(id)\
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}
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static const struct hpd_registers hpd_regs[] = {
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hpd_regs(0),
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hpd_regs(1),
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hpd_regs(2),
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hpd_regs(3),
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hpd_regs(4),
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hpd_regs(5),
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};
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static const struct hpd_sh_mask hpd_shift = {
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HPD_MASK_SH_LIST(__SHIFT)
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};
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static const struct hpd_sh_mask hpd_mask = {
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HPD_MASK_SH_LIST(_MASK)
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};
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#include "../ddc_regs.h"
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/* set field name */
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#define SF_DDC(reg_name, field_name, post_fix)\
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.field_name = reg_name ## __ ## field_name ## post_fix
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static const struct ddc_registers ddc_data_regs_dcn[] = {
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ddc_data_regs_dcn2(1),
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ddc_data_regs_dcn2(2),
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ddc_data_regs_dcn2(3),
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ddc_data_regs_dcn2(4),
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ddc_data_regs_dcn2(5),
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ddc_data_regs_dcn2(6),
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};
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static const struct ddc_registers ddc_clk_regs_dcn[] = {
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ddc_clk_regs_dcn2(1),
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ddc_clk_regs_dcn2(2),
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ddc_clk_regs_dcn2(3),
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ddc_clk_regs_dcn2(4),
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ddc_clk_regs_dcn2(5),
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ddc_clk_regs_dcn2(6),
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};
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static const struct ddc_sh_mask ddc_shift[] = {
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DDC_MASK_SH_LIST_DCN2(__SHIFT, 1),
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DDC_MASK_SH_LIST_DCN2(__SHIFT, 2),
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DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),
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DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),
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DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),
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DDC_MASK_SH_LIST_DCN2(__SHIFT, 6)
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};
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static const struct ddc_sh_mask ddc_mask[] = {
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DDC_MASK_SH_LIST_DCN2(_MASK, 1),
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DDC_MASK_SH_LIST_DCN2(_MASK, 2),
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DDC_MASK_SH_LIST_DCN2(_MASK, 3),
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DDC_MASK_SH_LIST_DCN2(_MASK, 4),
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DDC_MASK_SH_LIST_DCN2(_MASK, 5),
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DDC_MASK_SH_LIST_DCN2(_MASK, 6)
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};
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#include "../generic_regs.h"
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/* set field name */
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#define SF_GENERIC(reg_name, field_name, post_fix)\
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.field_name = reg_name ## __ ## field_name ## post_fix
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#define generic_regs(id) \
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{\
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GENERIC_REG_LIST(id)\
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}
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static const struct generic_registers generic_regs[] = {
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generic_regs(A),
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generic_regs(B),
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};
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static const struct generic_sh_mask generic_shift[] = {
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GENERIC_MASK_SH_LIST(__SHIFT, A),
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GENERIC_MASK_SH_LIST(__SHIFT, B),
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};
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static const struct generic_sh_mask generic_mask[] = {
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GENERIC_MASK_SH_LIST(_MASK, A),
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GENERIC_MASK_SH_LIST(_MASK, B),
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};
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static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)
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{
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struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin);
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generic->regs = &generic_regs[en];
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generic->shifts = &generic_shift[en];
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generic->masks = &generic_mask[en];
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generic->base.regs = &generic_regs[en].gpio;
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}
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static void define_ddc_registers(
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struct hw_gpio_pin *pin,
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uint32_t en)
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{
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struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
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switch (pin->id) {
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case GPIO_ID_DDC_DATA:
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ddc->regs = &ddc_data_regs_dcn[en];
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ddc->base.regs = &ddc_data_regs_dcn[en].gpio;
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break;
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case GPIO_ID_DDC_CLOCK:
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ddc->regs = &ddc_clk_regs_dcn[en];
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ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;
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break;
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default:
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ASSERT_CRITICAL(false);
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return;
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}
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ddc->shifts = &ddc_shift[en];
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ddc->masks = &ddc_mask[en];
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}
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static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
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{
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struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
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hpd->regs = &hpd_regs[en];
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hpd->shifts = &hpd_shift;
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hpd->masks = &hpd_mask;
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hpd->base.regs = &hpd_regs[en].gpio;
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}
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/* fucntion table */
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static const struct hw_factory_funcs funcs = {
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.init_ddc_data = dal_hw_ddc_init,
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.init_generic = dal_hw_generic_init,
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.init_hpd = dal_hw_hpd_init,
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.get_ddc_pin = dal_hw_ddc_get_pin,
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.get_hpd_pin = dal_hw_hpd_get_pin,
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.get_generic_pin = dal_hw_generic_get_pin,
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.define_hpd_registers = define_hpd_registers,
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.define_ddc_registers = define_ddc_registers,
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.define_generic_registers = define_generic_registers
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};
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/*
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* dal_hw_factory_dcn10_init
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*
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* @brief
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* Initialize HW factory function pointers and pin info
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*
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* @param
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* struct hw_factory *factory - [out] struct of function pointers
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*/
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void dal_hw_factory_dcn30_init(struct hw_factory *factory)
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{
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/*TODO check ASIC CAPs*/
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factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
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factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
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factory->number_of_pins[GPIO_ID_GENERIC] = 4;
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factory->number_of_pins[GPIO_ID_HPD] = 6;
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factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28;
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factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
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factory->number_of_pins[GPIO_ID_SYNC] = 0;
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factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/
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factory->funcs = &funcs;
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}
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#endif
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@ -0,0 +1,33 @@
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/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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#ifndef __DAL_HW_FACTORY_DCN30_H__
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#define __DAL_HW_FACTORY_DCN30_H__
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/* Initialize HW factory function pointers and pin info */
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void dal_hw_factory_dcn30_init(struct hw_factory *factory);
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#endif /* __DAL_HW_FACTORY_DCN30_H__ */
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#endif
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@ -0,0 +1,387 @@
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/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
|
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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/*
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* Pre-requisites: headers required by header of this unit
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*/
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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#include "hw_translate_dcn30.h"
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#include "dm_services.h"
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#include "include/gpio_types.h"
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#include "../hw_translate.h"
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#include "sienna_cichlid_ip_offset.h"
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#include "dcn/dcn_3_0_0_offset.h"
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#include "dcn/dcn_3_0_0_sh_mask.h"
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#include "nbio/nbio_7_4_offset.h"
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#include "dcn/dpcs_3_0_0_offset.h"
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#include "dcn/dpcs_3_0_0_sh_mask.h"
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#include "mmhub/mmhub_2_0_0_offset.h"
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#include "mmhub/mmhub_2_0_0_sh_mask.h"
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/* begin *********************
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* macros to expend register list macro defined in HW object header file */
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/* DCN */
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#define block HPD
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#define reg_num 0
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#undef BASE_INNER
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#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
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#define BASE(seg) BASE_INNER(seg)
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#undef REG
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#define REG(reg_name)\
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BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
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#define SF_HPD(reg_name, field_name, post_fix)\
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.field_name = reg_name ## __ ## field_name ## post_fix
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/* macros to expend register list macro defined in HW object header file
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* end *********************/
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static bool offset_to_id(
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uint32_t offset,
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uint32_t mask,
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enum gpio_id *id,
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uint32_t *en)
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{
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switch (offset) {
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/* GENERIC */
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case REG(DC_GPIO_GENERIC_A):
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*id = GPIO_ID_GENERIC;
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switch (mask) {
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case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
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*en = GPIO_GENERIC_A;
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return true;
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case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:
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*en = GPIO_GENERIC_B;
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return true;
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case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:
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*en = GPIO_GENERIC_C;
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return true;
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case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:
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*en = GPIO_GENERIC_D;
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return true;
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case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:
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*en = GPIO_GENERIC_E;
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return true;
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case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:
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*en = GPIO_GENERIC_F;
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return true;
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case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK:
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*en = GPIO_GENERIC_G;
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return true;
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default:
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ASSERT_CRITICAL(false);
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return false;
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}
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break;
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/* HPD */
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case REG(DC_GPIO_HPD_A):
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*id = GPIO_ID_HPD;
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switch (mask) {
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case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:
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*en = GPIO_HPD_1;
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return true;
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case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:
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*en = GPIO_HPD_2;
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return true;
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case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:
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*en = GPIO_HPD_3;
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return true;
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case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:
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*en = GPIO_HPD_4;
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return true;
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case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:
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*en = GPIO_HPD_5;
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return true;
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case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK:
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*en = GPIO_HPD_6;
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return true;
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default:
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ASSERT_CRITICAL(false);
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return false;
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}
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break;
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/* REG(DC_GPIO_GENLK_MASK */
|
||||
case REG(DC_GPIO_GENLK_A):
|
||||
*id = GPIO_ID_GSL;
|
||||
switch (mask) {
|
||||
case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:
|
||||
*en = GPIO_GSL_GENLOCK_CLOCK;
|
||||
return true;
|
||||
case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:
|
||||
*en = GPIO_GSL_GENLOCK_VSYNC;
|
||||
return true;
|
||||
case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:
|
||||
*en = GPIO_GSL_SWAPLOCK_A;
|
||||
return true;
|
||||
case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:
|
||||
*en = GPIO_GSL_SWAPLOCK_B;
|
||||
return true;
|
||||
default:
|
||||
ASSERT_CRITICAL(false);
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
/* DDC */
|
||||
/* we don't care about the GPIO_ID for DDC
|
||||
* in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
|
||||
* directly in the create method */
|
||||
case REG(DC_GPIO_DDC1_A):
|
||||
*en = GPIO_DDC_LINE_DDC1;
|
||||
return true;
|
||||
case REG(DC_GPIO_DDC2_A):
|
||||
*en = GPIO_DDC_LINE_DDC2;
|
||||
return true;
|
||||
case REG(DC_GPIO_DDC3_A):
|
||||
*en = GPIO_DDC_LINE_DDC3;
|
||||
return true;
|
||||
case REG(DC_GPIO_DDC4_A):
|
||||
*en = GPIO_DDC_LINE_DDC4;
|
||||
return true;
|
||||
case REG(DC_GPIO_DDC5_A):
|
||||
*en = GPIO_DDC_LINE_DDC5;
|
||||
return true;
|
||||
case REG(DC_GPIO_DDC6_A):
|
||||
*en = GPIO_DDC_LINE_DDC6;
|
||||
return true;
|
||||
case REG(DC_GPIO_DDCVGA_A):
|
||||
*en = GPIO_DDC_LINE_DDC_VGA;
|
||||
return true;
|
||||
|
||||
// case REG(DC_GPIO_I2CPAD_A): not exit
|
||||
// case REG(DC_GPIO_PWRSEQ_A):
|
||||
// case REG(DC_GPIO_PAD_STRENGTH_1):
|
||||
// case REG(DC_GPIO_PAD_STRENGTH_2):
|
||||
// case REG(DC_GPIO_DEBUG):
|
||||
/* UNEXPECTED */
|
||||
default:
|
||||
// case REG(DC_GPIO_SYNCA_A): not exist
|
||||
ASSERT_CRITICAL(false);
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
static bool id_to_offset(
|
||||
enum gpio_id id,
|
||||
uint32_t en,
|
||||
struct gpio_pin_info *info)
|
||||
{
|
||||
bool result = true;
|
||||
|
||||
switch (id) {
|
||||
case GPIO_ID_DDC_DATA:
|
||||
info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK;
|
||||
switch (en) {
|
||||
case GPIO_DDC_LINE_DDC1:
|
||||
info->offset = REG(DC_GPIO_DDC1_A);
|
||||
break;
|
||||
case GPIO_DDC_LINE_DDC2:
|
||||
info->offset = REG(DC_GPIO_DDC2_A);
|
||||
break;
|
||||
case GPIO_DDC_LINE_DDC3:
|
||||
info->offset = REG(DC_GPIO_DDC3_A);
|
||||
break;
|
||||
case GPIO_DDC_LINE_DDC4:
|
||||
info->offset = REG(DC_GPIO_DDC4_A);
|
||||
break;
|
||||
case GPIO_DDC_LINE_DDC5:
|
||||
info->offset = REG(DC_GPIO_DDC5_A);
|
||||
break;
|
||||
case GPIO_DDC_LINE_DDC6:
|
||||
info->offset = REG(DC_GPIO_DDC6_A);
|
||||
break;
|
||||
case GPIO_DDC_LINE_DDC_VGA:
|
||||
info->offset = REG(DC_GPIO_DDCVGA_A);
|
||||
break;
|
||||
case GPIO_DDC_LINE_I2C_PAD:
|
||||
default:
|
||||
ASSERT_CRITICAL(false);
|
||||
result = false;
|
||||
}
|
||||
break;
|
||||
case GPIO_ID_DDC_CLOCK:
|
||||
info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK;
|
||||
switch (en) {
|
||||
case GPIO_DDC_LINE_DDC1:
|
||||
info->offset = REG(DC_GPIO_DDC1_A);
|
||||
break;
|
||||
case GPIO_DDC_LINE_DDC2:
|
||||
info->offset = REG(DC_GPIO_DDC2_A);
|
||||
break;
|
||||
case GPIO_DDC_LINE_DDC3:
|
||||
info->offset = REG(DC_GPIO_DDC3_A);
|
||||
break;
|
||||
case GPIO_DDC_LINE_DDC4:
|
||||
info->offset = REG(DC_GPIO_DDC4_A);
|
||||
break;
|
||||
case GPIO_DDC_LINE_DDC5:
|
||||
info->offset = REG(DC_GPIO_DDC5_A);
|
||||
break;
|
||||
case GPIO_DDC_LINE_DDC6:
|
||||
info->offset = REG(DC_GPIO_DDC6_A);
|
||||
break;
|
||||
case GPIO_DDC_LINE_DDC_VGA:
|
||||
info->offset = REG(DC_GPIO_DDCVGA_A);
|
||||
break;
|
||||
case GPIO_DDC_LINE_I2C_PAD:
|
||||
default:
|
||||
ASSERT_CRITICAL(false);
|
||||
result = false;
|
||||
}
|
||||
break;
|
||||
case GPIO_ID_GENERIC:
|
||||
info->offset = REG(DC_GPIO_GENERIC_A);
|
||||
switch (en) {
|
||||
case GPIO_GENERIC_A:
|
||||
info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;
|
||||
break;
|
||||
case GPIO_GENERIC_B:
|
||||
info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;
|
||||
break;
|
||||
case GPIO_GENERIC_C:
|
||||
info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;
|
||||
break;
|
||||
case GPIO_GENERIC_D:
|
||||
info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;
|
||||
break;
|
||||
case GPIO_GENERIC_E:
|
||||
info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;
|
||||
break;
|
||||
case GPIO_GENERIC_F:
|
||||
info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;
|
||||
break;
|
||||
case GPIO_GENERIC_G:
|
||||
info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;
|
||||
break;
|
||||
default:
|
||||
ASSERT_CRITICAL(false);
|
||||
result = false;
|
||||
}
|
||||
break;
|
||||
case GPIO_ID_HPD:
|
||||
info->offset = REG(DC_GPIO_HPD_A);
|
||||
switch (en) {
|
||||
case GPIO_HPD_1:
|
||||
info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
|
||||
break;
|
||||
case GPIO_HPD_2:
|
||||
info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;
|
||||
break;
|
||||
case GPIO_HPD_3:
|
||||
info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;
|
||||
break;
|
||||
case GPIO_HPD_4:
|
||||
info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;
|
||||
break;
|
||||
case GPIO_HPD_5:
|
||||
info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;
|
||||
break;
|
||||
case GPIO_HPD_6:
|
||||
info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;
|
||||
break;
|
||||
default:
|
||||
ASSERT_CRITICAL(false);
|
||||
result = false;
|
||||
}
|
||||
break;
|
||||
case GPIO_ID_GSL:
|
||||
switch (en) {
|
||||
case GPIO_GSL_GENLOCK_CLOCK:
|
||||
/*not implmented*/
|
||||
ASSERT_CRITICAL(false);
|
||||
result = false;
|
||||
break;
|
||||
case GPIO_GSL_GENLOCK_VSYNC:
|
||||
/*not implmented*/
|
||||
ASSERT_CRITICAL(false);
|
||||
result = false;
|
||||
break;
|
||||
case GPIO_GSL_SWAPLOCK_A:
|
||||
/*not implmented*/
|
||||
ASSERT_CRITICAL(false);
|
||||
result = false;
|
||||
break;
|
||||
case GPIO_GSL_SWAPLOCK_B:
|
||||
/*not implmented*/
|
||||
ASSERT_CRITICAL(false);
|
||||
result = false;
|
||||
|
||||
break;
|
||||
default:
|
||||
ASSERT_CRITICAL(false);
|
||||
result = false;
|
||||
}
|
||||
break;
|
||||
case GPIO_ID_SYNC:
|
||||
case GPIO_ID_VIP_PAD:
|
||||
default:
|
||||
ASSERT_CRITICAL(false);
|
||||
result = false;
|
||||
}
|
||||
|
||||
if (result) {
|
||||
info->offset_y = info->offset + 2;
|
||||
info->offset_en = info->offset + 1;
|
||||
info->offset_mask = info->offset - 1;
|
||||
|
||||
info->mask_y = info->mask;
|
||||
info->mask_en = info->mask;
|
||||
info->mask_mask = info->mask;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/* function table */
|
||||
static const struct hw_translate_funcs funcs = {
|
||||
.offset_to_id = offset_to_id,
|
||||
.id_to_offset = id_to_offset,
|
||||
};
|
||||
|
||||
/*
|
||||
* dal_hw_translate_dcn10_init
|
||||
*
|
||||
* @brief
|
||||
* Initialize Hw translate function pointers.
|
||||
*
|
||||
* @param
|
||||
* struct hw_translate *tr - [out] struct of function pointers
|
||||
*
|
||||
*/
|
||||
void dal_hw_translate_dcn30_init(struct hw_translate *tr)
|
||||
{
|
||||
tr->funcs = &funcs;
|
||||
}
|
||||
|
||||
#endif
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* Copyright 2020 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
|
||||
#ifndef __DAL_HW_TRANSLATE_DCN30_H__
|
||||
#define __DAL_HW_TRANSLATE_DCN30_H__
|
||||
|
||||
struct hw_translate;
|
||||
|
||||
/* Initialize Hw translate function pointers */
|
||||
void dal_hw_translate_dcn30_init(struct hw_translate *tr);
|
||||
|
||||
#endif /* __DAL_HW_TRANSLATE_DCN30_H__ */
|
||||
#endif
|
|
@ -50,6 +50,9 @@
|
|||
#include "dcn20/hw_factory_dcn20.h"
|
||||
#include "dcn21/hw_factory_dcn21.h"
|
||||
#endif
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
|
||||
#include "dcn30/hw_factory_dcn30.h"
|
||||
#endif
|
||||
|
||||
#include "diagnostics/hw_factory_diag.h"
|
||||
|
||||
|
@ -99,7 +102,11 @@ bool dal_hw_factory_init(
|
|||
dal_hw_factory_dcn21_init(factory);
|
||||
return true;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
|
||||
case DCN_VERSION_3_0:
|
||||
dal_hw_factory_dcn30_init(factory);
|
||||
return true;
|
||||
#endif
|
||||
default:
|
||||
ASSERT_CRITICAL(false);
|
||||
return false;
|
||||
|
|
|
@ -48,6 +48,9 @@
|
|||
#include "dcn20/hw_translate_dcn20.h"
|
||||
#include "dcn21/hw_translate_dcn21.h"
|
||||
#endif
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
|
||||
#include "dcn30/hw_translate_dcn30.h"
|
||||
#endif
|
||||
|
||||
#include "diagnostics/hw_translate_diag.h"
|
||||
|
||||
|
@ -94,6 +97,11 @@ bool dal_hw_translate_init(
|
|||
dal_hw_translate_dcn21_init(translate);
|
||||
return true;
|
||||
#endif
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
|
||||
case DCN_VERSION_3_0:
|
||||
dal_hw_translate_dcn30_init(translate);
|
||||
return true;
|
||||
#endif
|
||||
|
||||
default:
|
||||
BREAK_TO_DEBUGGER();
|
||||
|
|
Loading…
Reference in New Issue