drm/i915/execlists: Use coherent writes into the context image
That we use a WB mapping for updating the RING_TAIL register inside the context image even on !llc machines has been a source of consternation for every reader. It appears to work on bsw+, but it may just have been that we have been incredibly bad at detecting the errors. v2: With extra enthusiasm. v3: Drop force of map type for pinned default_state as by the time we pin it, the map type is always WB and doesn't conflict with the earlier use by ce->state. v4: Transfer engine->default_state from MAP_WC to MAP_WB on creation so we do not need the MAP_FORCE littered around the backends Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180914123504.2062-3-chris@chris-wilson.co.uk
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@ -3096,6 +3096,12 @@ enum i915_map_type {
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I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
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I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
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};
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};
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static inline enum i915_map_type
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i915_coherent_map_type(struct drm_i915_private *i915)
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{
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return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
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}
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/**
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/**
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* i915_gem_object_pin_map - return a contiguous mapping of the entire object
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* i915_gem_object_pin_map - return a contiguous mapping of the entire object
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* @obj: the object to map into kernel address space
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* @obj: the object to map into kernel address space
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@ -5418,6 +5418,8 @@ static int __intel_engines_record_defaults(struct drm_i915_private *i915)
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struct i915_vma *state;
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struct i915_vma *state;
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void *vaddr;
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void *vaddr;
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GEM_BUG_ON(to_intel_context(ctx, engine)->pin_count);
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state = to_intel_context(ctx, engine)->state;
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state = to_intel_context(ctx, engine)->state;
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if (!state)
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if (!state)
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continue;
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continue;
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@ -5442,7 +5444,7 @@ static int __intel_engines_record_defaults(struct drm_i915_private *i915)
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/* Check we can acquire the image of the context state */
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/* Check we can acquire the image of the context state */
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vaddr = i915_gem_object_pin_map(engine->default_state,
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vaddr = i915_gem_object_pin_map(engine->default_state,
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I915_MAP_WB);
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I915_MAP_FORCE_WB);
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if (IS_ERR(vaddr)) {
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if (IS_ERR(vaddr)) {
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err = PTR_ERR(vaddr);
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err = PTR_ERR(vaddr);
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goto err_active;
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goto err_active;
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@ -1707,6 +1707,7 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv,
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const struct i915_oa_config *oa_config)
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const struct i915_oa_config *oa_config)
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{
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{
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struct intel_engine_cs *engine = dev_priv->engine[RCS];
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struct intel_engine_cs *engine = dev_priv->engine[RCS];
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unsigned int map_type = i915_coherent_map_type(dev_priv);
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struct i915_gem_context *ctx;
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struct i915_gem_context *ctx;
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struct i915_request *rq;
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struct i915_request *rq;
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int ret;
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int ret;
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@ -1741,7 +1742,7 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv,
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if (!ce->state)
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if (!ce->state)
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continue;
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continue;
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regs = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
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regs = i915_gem_object_pin_map(ce->state->obj, map_type);
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if (IS_ERR(regs))
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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return PTR_ERR(regs);
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@ -1294,7 +1294,7 @@ static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma)
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* on an active context (which by nature is already on the GPU).
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* on an active context (which by nature is already on the GPU).
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*/
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*/
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if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
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if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
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err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
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err = i915_gem_object_set_to_wc_domain(vma->obj, true);
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if (err)
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if (err)
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return err;
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return err;
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}
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}
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@ -1322,7 +1322,9 @@ __execlists_context_pin(struct intel_engine_cs *engine,
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if (ret)
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if (ret)
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goto err;
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goto err;
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vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
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vaddr = i915_gem_object_pin_map(ce->state->obj,
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i915_coherent_map_type(ctx->i915) |
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I915_MAP_OVERRIDE);
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if (IS_ERR(vaddr)) {
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if (IS_ERR(vaddr)) {
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ret = PTR_ERR(vaddr);
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ret = PTR_ERR(vaddr);
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goto unpin_vma;
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goto unpin_vma;
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