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Renesas ARM64 DT updates for v5.5 

- Support for the RZ/G2N (r8a774b1) SoC and the HiHope RZ/G2N board,
   - CPU idle support for R-Car H3 and M3-W,
   - LVDS and backlight support on the HiHope RZ/G2M and RZ/G2N boards,
     with Advantech idk-1110wr LVDS panel,
   - Minor fixes and improvements.
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Merge tag 'renesas-arm64-dt-for-v5.5-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM64 DT updates for v5.5

  - Support for the RZ/G2N (r8a774b1) SoC and the HiHope RZ/G2N board,
  - CPU idle support for R-Car H3 and M3-W,
  - LVDS and backlight support on the HiHope RZ/G2M and RZ/G2N boards,
    with Advantech idk-1110wr LVDS panel,
  - Minor fixes and improvements.

* tag 'renesas-arm64-dt-for-v5.5-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (50 commits)
  arm64: dts: renesas: r8a774b1: Add CAN and CAN FD support
  arm64: dts: renesas: Add iommus to R-Car Gen3 SDHI/MMC nodes
  arm64: dts: renesas: r8a774b1: Add INTC-EX device node
  arm64: dts: renesas: r8a774b1: Add USB3.0 device nodes
  arm64: dts: renesas: r8a774b1: Add USB-DMAC and HSUSB device nodes
  arm64: dts: renesas: r8a774b1: Add USB2.0 phy and host (EHCI/OHCI) device nodes
  arm64: dts: renesas: r8a774b1: Add Sound and Audio DMAC device nodes
  arm64: dts: renesas: hihope-rzg2-ex: Let the board specific DT decide about pciec1
  arm64: dts: renesas: r8a774b1: Add PCIe device nodes
  arm64: dts: renesas: r8a774b1: Add all MSIOF nodes
  arm64: dts: renesas: r8a774b1: Add RWDT node
  arm64: dts: renesas: Add support for Advantech idk-1110wr LVDS panel
  arm64: dts: renesas: hihope-rzg2-ex: Add LVDS support
  arm64: dts: renesas: hihope-rzg2-ex: Enable backlight
  arm64: dts: renesas: r8a774b1: Add PWM device nodes
  arm64: dts: renesas: r8a774b1: Add FDP1 device nodes
  arm64: dts: renesas: r8a774b1-hihope-rzg2n: Add display clock properties
  arm64: dts: renesas: r8a774b1: Add HDMI encoder instance
  arm64: dts: renesas: r8a774b1: Add DU device to DT
  arm64: dts: renesas: hihope-common: Move du clk properties out of common dtsi
  ...

Link: https://lore.kernel.org/r/20191018101136.26350-4-geert+renesas@glider.be
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-10-21 14:35:51 -07:00
parent aca95ea77c 3fa08cbb06
commit 662be40034
21 changed files with 2603 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm64/boot/dts/renesas/Makefile
View File

@ -1,6 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m.dtb
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex.dtb
dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb r8a774c0-ek874.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb

28
arch/arm64/boot/dts/renesas/hihope-common.dtsi
View File

@ -86,7 +86,7 @@
label = "rcar-sound";
dais = <&rsnd_port0>;
dais = <&rsnd_port>;
};
vbus0_usb2: regulator-vbus0-usb2 {
@ -142,14 +142,6 @@
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&versaclock5 1>,
<&x302_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
status = "okay";
};
@ -191,7 +183,7 @@
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint0>;
remote-endpoint = <&rsnd_endpoint>;
};
};
};
@ -327,17 +319,15 @@
/* Single DAI */
#sound-dai-cells = <0>;
ports {
rsnd_port0: port@0 {
rsnd_endpoint0: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
rsnd_port: port {
rsnd_endpoint: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint0>;
frame-master = <&rsnd_endpoint0>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint>;
frame-master = <&rsnd_endpoint>;
playback = <&ssi2>;
};
playback = <&ssi2>;
};
};
};

51
arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
View File

@ -13,6 +13,14 @@
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm0 0 50000>;
brightness-levels = <0 2 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
};
&avb {
@ -43,11 +51,36 @@
status = "okay";
};
&pciec0 {
status = "okay";
&gpio1 {
/*
* When GP1_20 is LOW LVDS0 is connected to the LVDS connector
* When GP1_20 is HIGH LVDS0 is connected to the LT8918L
*/
lvds-connector-en-gpio {
gpio-hog;
gpios = <20 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "lvds-connector-en-gpio";
};
};
&pciec1 {
&lvds0 {
/*
* Please include the LVDS panel .dtsi file and uncomment the below line
* to enable LVDS panel connected to RZ/G2[MN] boards.
*/
/* status = "okay"; */
ports {
port@1 {
lvds_connector: endpoint {
};
};
};
};
&pciec0 {
status = "okay";
};
@ -82,4 +115,16 @@
groups = "can1_data";
function = "can1";
};
pwm0_pins: pwm0 {
groups = "pwm0";
function = "pwm0";
};
};
&pwm0 {
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
status = "okay";
};

4
arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts
View File

@ -13,3 +13,7 @@
compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2m",
"renesas,r8a774a1";
};
&pciec1 {
status = "okay";
};

11
arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m.dts
View File

@ -24,3 +24,14 @@
reg = <0x6 0x00000000 0x0 0x80000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&versaclock5 1>,
<&x302_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};

13
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
View File

@ -1726,17 +1726,6 @@
"ssi.1", "ssi.0";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
};
};
rcar_sound,ctu {
ctu00: ctu-0 { };
ctu01: ctu-1 { };
@ -2651,7 +2640,7 @@
clock-names = "du.0", "du.1", "du.2";
status = "disabled";
vsps = <&vspd0 &vspd1 &vspd2>;
vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
ports {
#address-cells = <1>;

15
arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex.dts Normal file
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2N sub board
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
#include "r8a774b1-hihope-rzg2n.dts"
#include "hihope-rzg2-ex.dtsi"
/ {
model = "HopeRun HiHope RZ/G2N with sub board";
compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2n",
"renesas,r8a774b1";
};

41
arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n.dts Normal file
View File

@ -0,0 +1,41 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2N main board
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a774b1.dtsi"
#include "hihope-common.dtsi"
/ {
model = "HopeRun HiHope RZ/G2N main board based on r8a774b1";
compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x0 0x80000000>;
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 721>,
<&versaclock5 1>,
<&x302_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
&sdhi3 {
mmc-hs400-1_8v;
};

2250
arch/arm64/boot/dts/renesas/r8a774b1.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

20
arch/arm64/boot/dts/renesas/r8a774c0.dtsi
View File

@ -73,9 +73,11 @@
compatible = "arm,cortex-a53";
reg = <0>;
device_type = "cpu";
#cooling-cells = <2>;
power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
dynamic-power-coefficient = <277>;
clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
};
@ -1905,18 +1907,30 @@
thermal-zones {
cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&thermal>;
polling-delay = <0>;
thermal-sensors = <&thermal 0>;
sustainable-power = <717>;
cooling-maps {
map0 {
trip = <&target>;
cooling-device = <&a53_0 0 2>;
contribution = <1024>;
};
};
trips {
cpu-crit {
sensor1_crit: sensor1-crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
target: trip-point1 {
temperature = <100000>;
hysteresis = <2000>;
type = "passive";
};
};
};
};

2
arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
View File

@ -30,7 +30,7 @@
};
&du {
vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;
vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd3 0>;
};
&fcpvb1 {

34
arch/arm64/boot/dts/renesas/r8a7795.dtsi
View File

@ -155,6 +155,7 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
dynamic-power-coefficient = <854>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
@ -169,6 +170,7 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
@ -182,6 +184,7 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
@ -195,6 +198,7 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
@ -208,6 +212,7 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_1>;
#cooling-cells = <2>;
dynamic-power-coefficient = <277>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
@ -222,6 +227,7 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_1>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
@ -234,6 +240,7 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_1>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
@ -246,6 +253,7 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_1>;
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
@ -264,6 +272,28 @@
cache-unified;
cache-level = <2>;
};
idle-states {
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
entry-latency-us = <400>;
exit-latency-us = <500>;
min-residency-us = <4000>;
};
CPU_SLEEP_1: cpu-sleep-1 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
entry-latency-us = <700>;
exit-latency-us = <700>;
min-residency-us = <5000>;
};
};
};
extal_clk: extal {
@ -2569,6 +2599,7 @@
max-frequency = <200000000>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 314>;
iommus = <&ipmmu_ds1 32>;
status = "disabled";
};
@ -2581,6 +2612,7 @@
max-frequency = <200000000>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 313>;
iommus = <&ipmmu_ds1 33>;
status = "disabled";
};
@ -2593,6 +2625,7 @@
max-frequency = <200000000>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 312>;
iommus = <&ipmmu_ds1 34>;
status = "disabled";
};
@ -2605,6 +2638,7 @@
max-frequency = <200000000>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 311>;
iommus = <&ipmmu_ds1 35>;
status = "disabled";
};

34
arch/arm64/boot/dts/renesas/r8a7796.dtsi
View File

@ -160,6 +160,7 @@
power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
dynamic-power-coefficient = <854>;
clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
@ -174,6 +175,7 @@
power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
operating-points-v2 = <&cluster0_opp>;
capacity-dmips-mhz = <1024>;
@ -187,6 +189,7 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_1>;
#cooling-cells = <2>;
dynamic-power-coefficient = <277>;
clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
@ -201,6 +204,7 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_1>;
clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
@ -213,6 +217,7 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_1>;
clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
@ -225,6 +230,7 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_1>;
clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
@ -243,6 +249,28 @@
cache-unified;
cache-level = <2>;
};
idle-states {
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
entry-latency-us = <400>;
exit-latency-us = <500>;
min-residency-us = <4000>;
};
CPU_SLEEP_1: cpu-sleep-1 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
entry-latency-us = <700>;
exit-latency-us = <700>;
min-residency-us = <5000>;
};
};
};
extal_clk: extal {
@ -2366,6 +2394,7 @@
max-frequency = <200000000>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 314>;
iommus = <&ipmmu_ds1 32>;
status = "disabled";
};
@ -2378,6 +2407,7 @@
max-frequency = <200000000>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 313>;
iommus = <&ipmmu_ds1 33>;
status = "disabled";
};
@ -2390,6 +2420,7 @@
max-frequency = <200000000>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 312>;
iommus = <&ipmmu_ds1 34>;
status = "disabled";
};
@ -2402,6 +2433,7 @@
max-frequency = <200000000>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 311>;
iommus = <&ipmmu_ds1 35>;
status = "disabled";
};
@ -2765,7 +2797,7 @@
clock-names = "du.0", "du.1", "du.2";
status = "disabled";
vsps = <&vspd0 &vspd1 &vspd2>;
vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
ports {
#address-cells = <1>;

4
arch/arm64/boot/dts/renesas/r8a77965.dtsi
View File

@ -2105,6 +2105,7 @@
max-frequency = <200000000>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 314>;
iommus = <&ipmmu_ds1 32>;
status = "disabled";
};
@ -2117,6 +2118,7 @@
max-frequency = <200000000>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 313>;
iommus = <&ipmmu_ds1 33>;
status = "disabled";
};
@ -2129,6 +2131,7 @@
max-frequency = <200000000>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 312>;
iommus = <&ipmmu_ds1 34>;
status = "disabled";
};
@ -2141,6 +2144,7 @@
max-frequency = <200000000>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 311>;
iommus = <&ipmmu_ds1 35>;
status = "disabled";
};

5
arch/arm64/boot/dts/renesas/r8a77970.dtsi
View File

@ -652,7 +652,7 @@
};
pwm3: pwm@e6e33000 {
compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
reg = <0 0xe6e33000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
@ -1035,6 +1035,7 @@
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 314>;
max-frequency = <200000000>;
iommus = <&ipmmu_ds1 32>;
status = "disabled";
};
@ -1120,7 +1121,7 @@
clock-names = "du.0";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 724>;
vsps = <&vspd0>;
vsps = <&vspd0 0>;
status = "disabled";
ports {

3
arch/arm64/boot/dts/renesas/r8a77980.dtsi
View File

@ -1338,6 +1338,7 @@
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 314>;
max-frequency = <200000000>;
iommus = <&ipmmu_ds1 32>;
status = "disabled";
};
@ -1495,7 +1496,7 @@
clock-names = "du.0";
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 724>;
vsps = <&vspd0>;
vsps = <&vspd0 0>;
status = "disabled";
ports {

3
arch/arm64/boot/dts/renesas/r8a77990.dtsi
View File

@ -1580,6 +1580,7 @@
max-frequency = <200000000>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 314>;
iommus = <&ipmmu_ds1 32>;
status = "disabled";
};
@ -1592,6 +1593,7 @@
max-frequency = <200000000>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 313>;
iommus = <&ipmmu_ds1 33>;
status = "disabled";
};
@ -1604,6 +1606,7 @@
max-frequency = <200000000>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 311>;
iommus = <&ipmmu_ds1 35>;
status = "disabled";
};

1
arch/arm64/boot/dts/renesas/r8a77995.dtsi
View File

@ -916,6 +916,7 @@
max-frequency = <200000000>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 312>;
iommus = <&ipmmu_ds1 34>;
status = "disabled";
};

41
arch/arm64/boot/dts/renesas/rzg2-advantech-idk-1110wr-panel.dtsi Normal file
View File

@ -0,0 +1,41 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Advantech idk-1110wr LVDS panel connected
* to RZ/G2 boards
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
/ {
panel-lvds {
compatible = "advantech,idk-1110wr", "panel-lvds";
width-mm = <223>;
height-mm = <125>;
data-mapping = "jeida-24";
panel-timing {
/* 1024x600 @60Hz */
clock-frequency = <51200000>;
hactive = <1024>;
vactive = <600>;
hsync-len = <240>;
hfront-porch = <40>;
hback-porch = <40>;
vfront-porch = <15>;
vback-porch = <10>;
vsync-len = <10>;
};
port {
panel_in: endpoint {
remote-endpoint = <&lvds_connector>;
};
};
};
};
&lvds_connector {
remote-endpoint = <&panel_in>;
};

57
include/dt-bindings/clock/r8a774b1-cpg-mssr.h Normal file
View File

@ -0,0 +1,57 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a774b1 CPG Core Clocks */
#define R8A774B1_CLK_Z 0
#define R8A774B1_CLK_ZG 1
#define R8A774B1_CLK_ZTR 2
#define R8A774B1_CLK_ZTRD2 3
#define R8A774B1_CLK_ZT 4
#define R8A774B1_CLK_ZX 5
#define R8A774B1_CLK_S0D1 6
#define R8A774B1_CLK_S0D2 7
#define R8A774B1_CLK_S0D3 8
#define R8A774B1_CLK_S0D4 9
#define R8A774B1_CLK_S0D6 10
#define R8A774B1_CLK_S0D8 11
#define R8A774B1_CLK_S0D12 12
#define R8A774B1_CLK_S1D2 13
#define R8A774B1_CLK_S1D4 14
#define R8A774B1_CLK_S2D1 15
#define R8A774B1_CLK_S2D2 16
#define R8A774B1_CLK_S2D4 17
#define R8A774B1_CLK_S3D1 18
#define R8A774B1_CLK_S3D2 19
#define R8A774B1_CLK_S3D4 20
#define R8A774B1_CLK_LB 21
#define R8A774B1_CLK_CL 22
#define R8A774B1_CLK_ZB3 23
#define R8A774B1_CLK_ZB3D2 24
#define R8A774B1_CLK_CR 25
#define R8A774B1_CLK_DDR 26
#define R8A774B1_CLK_SD0H 27
#define R8A774B1_CLK_SD0 28
#define R8A774B1_CLK_SD1H 29
#define R8A774B1_CLK_SD1 30
#define R8A774B1_CLK_SD2H 31
#define R8A774B1_CLK_SD2 32
#define R8A774B1_CLK_SD3H 33
#define R8A774B1_CLK_SD3 34
#define R8A774B1_CLK_RPC 35
#define R8A774B1_CLK_RPCD2 36
#define R8A774B1_CLK_MSO 37
#define R8A774B1_CLK_HDMI 38
#define R8A774B1_CLK_CSI0 39
#define R8A774B1_CLK_CP 40
#define R8A774B1_CLK_CPEX 41
#define R8A774B1_CLK_R 42
#define R8A774B1_CLK_OSC 43
#define R8A774B1_CLK_CANFD 44
#endif /* __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ */

26
include/dt-bindings/power/r8a774b1-sysc.h Normal file
View File

@ -0,0 +1,26 @@
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright (C) 2019 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_R8A774B1_SYSC_H__
#define __DT_BINDINGS_POWER_R8A774B1_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A774B1_PD_CA57_CPU0 0
#define R8A774B1_PD_CA57_CPU1 1
#define R8A774B1_PD_A3VP 9
#define R8A774B1_PD_CA57_SCU 12
#define R8A774B1_PD_A3VC 14
#define R8A774B1_PD_3DG_A 17
#define R8A774B1_PD_3DG_B 18
#define R8A774B1_PD_A2VC1 26
/* Always-on power area */
#define R8A774B1_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ */