[SCSI] megaraid_sas: add new controllers (0x78 0x79)
Add the new controllers (0x78 0x79) support to the driver. Those controllers are LSI's next generation (gen2) SAS controllers. [akpm@linux-foundation.org: coding-style fixes] [akpm@linux-foundation.org: parenthesise a macro] Signed-off-by: Bo Yang <bo.yang@lsi.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
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@ -10,7 +10,7 @@
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* 2 of the License, or (at your option) any later version.
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* 2 of the License, or (at your option) any later version.
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*
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*
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* FILE : megaraid_sas.c
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* FILE : megaraid_sas.c
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* Version : v00.00.03.20-rc1
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* Version : v00.00.04.01-rc1
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*
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*
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* Authors:
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* Authors:
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* (email-id : megaraidlinux@lsi.com)
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* (email-id : megaraidlinux@lsi.com)
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@ -71,6 +71,10 @@ static struct pci_device_id megasas_pci_table[] = {
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/* ppc IOP */
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/* ppc IOP */
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{PCI_DEVICE(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_SAS1078DE)},
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{PCI_DEVICE(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_SAS1078DE)},
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/* ppc IOP */
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/* ppc IOP */
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{PCI_DEVICE(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_SAS1078GEN2)},
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/* gen2*/
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{PCI_DEVICE(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_SAS0079GEN2)},
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/* gen2*/
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{PCI_DEVICE(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_VERDE_ZCR)},
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{PCI_DEVICE(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_VERDE_ZCR)},
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/* xscale IOP, vega */
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/* xscale IOP, vega */
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{PCI_DEVICE(PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_PERC5)},
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{PCI_DEVICE(PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_PERC5)},
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@ -323,6 +327,99 @@ static struct megasas_instance_template megasas_instance_template_ppc = {
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.read_fw_status_reg = megasas_read_fw_status_reg_ppc,
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.read_fw_status_reg = megasas_read_fw_status_reg_ppc,
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};
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};
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/**
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* The following functions are defined for gen2 (deviceid : 0x78 0x79)
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* controllers
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*/
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/**
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* megasas_enable_intr_gen2 - Enables interrupts
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* @regs: MFI register set
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*/
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static inline void
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megasas_enable_intr_gen2(struct megasas_register_set __iomem *regs)
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{
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writel(0xFFFFFFFF, &(regs)->outbound_doorbell_clear);
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/* write ~0x00000005 (4 & 1) to the intr mask*/
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writel(~MFI_GEN2_ENABLE_INTERRUPT_MASK, &(regs)->outbound_intr_mask);
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/* Dummy readl to force pci flush */
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readl(®s->outbound_intr_mask);
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}
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/**
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* megasas_disable_intr_gen2 - Disables interrupt
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* @regs: MFI register set
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*/
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static inline void
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megasas_disable_intr_gen2(struct megasas_register_set __iomem *regs)
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{
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u32 mask = 0xFFFFFFFF;
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writel(mask, ®s->outbound_intr_mask);
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/* Dummy readl to force pci flush */
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readl(®s->outbound_intr_mask);
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}
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/**
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* megasas_read_fw_status_reg_gen2 - returns the current FW status value
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* @regs: MFI register set
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*/
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static u32
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megasas_read_fw_status_reg_gen2(struct megasas_register_set __iomem *regs)
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{
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return readl(&(regs)->outbound_scratch_pad);
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}
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/**
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* megasas_clear_interrupt_gen2 - Check & clear interrupt
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* @regs: MFI register set
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*/
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static int
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megasas_clear_intr_gen2(struct megasas_register_set __iomem *regs)
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{
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u32 status;
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/*
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* Check if it is our interrupt
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*/
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status = readl(®s->outbound_intr_status);
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if (!(status & MFI_GEN2_ENABLE_INTERRUPT_MASK))
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return 1;
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/*
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* Clear the interrupt by writing back the same value
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*/
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writel(status, ®s->outbound_doorbell_clear);
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/* Dummy readl to force pci flush */
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readl(®s->outbound_intr_status);
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return 0;
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}
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/**
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* megasas_fire_cmd_gen2 - Sends command to the FW
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* @frame_phys_addr : Physical address of cmd
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* @frame_count : Number of frames for the command
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* @regs : MFI register set
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*/
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static inline void
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megasas_fire_cmd_gen2(dma_addr_t frame_phys_addr, u32 frame_count,
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struct megasas_register_set __iomem *regs)
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{
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writel((frame_phys_addr | (frame_count<<1))|1,
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&(regs)->inbound_queue_port);
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}
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static struct megasas_instance_template megasas_instance_template_gen2 = {
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.fire_cmd = megasas_fire_cmd_gen2,
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.enable_intr = megasas_enable_intr_gen2,
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.disable_intr = megasas_disable_intr_gen2,
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.clear_intr = megasas_clear_intr_gen2,
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.read_fw_status_reg = megasas_read_fw_status_reg_gen2,
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};
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/**
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/**
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* This is the end of set of functions & definitions
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* This is the end of set of functions & definitions
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* specific to ppc (deviceid : 0x60) controllers
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* specific to ppc (deviceid : 0x60) controllers
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@ -1982,7 +2079,12 @@ static int megasas_init_mfi(struct megasas_instance *instance)
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/*
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/*
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* Map the message registers
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* Map the message registers
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*/
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*/
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if ((instance->pdev->device == PCI_DEVICE_ID_LSI_SAS1078GEN2) ||
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(instance->pdev->device == PCI_DEVICE_ID_LSI_SAS0079GEN2)) {
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instance->base_addr = pci_resource_start(instance->pdev, 1);
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} else {
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instance->base_addr = pci_resource_start(instance->pdev, 0);
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instance->base_addr = pci_resource_start(instance->pdev, 0);
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}
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if (pci_request_regions(instance->pdev, "megasas: LSI")) {
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if (pci_request_regions(instance->pdev, "megasas: LSI")) {
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printk(KERN_DEBUG "megasas: IO memory region busy!\n");
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printk(KERN_DEBUG "megasas: IO memory region busy!\n");
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@ -2004,6 +2106,10 @@ static int megasas_init_mfi(struct megasas_instance *instance)
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case PCI_DEVICE_ID_LSI_SAS1078DE:
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case PCI_DEVICE_ID_LSI_SAS1078DE:
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instance->instancet = &megasas_instance_template_ppc;
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instance->instancet = &megasas_instance_template_ppc;
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break;
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break;
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case PCI_DEVICE_ID_LSI_SAS1078GEN2:
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case PCI_DEVICE_ID_LSI_SAS0079GEN2:
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instance->instancet = &megasas_instance_template_gen2;
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break;
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case PCI_DEVICE_ID_LSI_SAS1064R:
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case PCI_DEVICE_ID_LSI_SAS1064R:
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case PCI_DEVICE_ID_DELL_PERC5:
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case PCI_DEVICE_ID_DELL_PERC5:
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default:
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default:
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@ -28,6 +28,8 @@
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#define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
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#define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
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#define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
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#define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
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#define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
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#define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
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#define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
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#define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
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/*
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/*
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* =====================================
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* =====================================
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@ -580,6 +582,8 @@ struct megasas_ctrl_info {
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#define MEGASAS_COMPLETION_TIMER_INTERVAL (HZ/10)
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#define MEGASAS_COMPLETION_TIMER_INTERVAL (HZ/10)
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#define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
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#define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
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#define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
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#define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
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/*
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/*
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* register set for both 1068 and 1078 controllers
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* register set for both 1068 and 1078 controllers
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