drm: panel: Add Himax HX8394 panel controller driver
The driver is for panels based on the Himax HX8394 controller, such as the HannStar HSD060BHW4 720x1440 TFT LCD panel that uses a MIPI-DSI interface. Signed-off-by: Kamil Trzciński <ayufan@ayufan.eu> Co-developed-by: Ondrej Jirman <megi@xff.cz> Signed-off-by: Ondrej Jirman <megi@xff.cz> Co-developed-by: Javier Martinez Canillas <javierm@redhat.com> Signed-off-by: Javier Martinez Canillas <javierm@redhat.com> Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Tested-by: Tom Fitzhenry <tom@tom-fitzhenry.me.uk> Tested-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230102230733.3506624-3-javierm@redhat.com
This commit is contained in:
Kamil Trzciński
Linus Walleij
parent
3b0c2b2b52
commit
65dc9360f7
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@ -154,6 +154,18 @@ config DRM_PANEL_FEIYANG_FY07024DI26A30D
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Say Y if you want to enable support for panels based on the
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Feiyang FY07024DI26A30-D MIPI-DSI interface.
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config DRM_PANEL_HIMAX_HX8394
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tristate "HIMAX HX8394 MIPI-DSI LCD panels"
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depends on OF
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depends on DRM_MIPI_DSI
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depends on BACKLIGHT_CLASS_DEVICE
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help
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Say Y if you want to enable support for panels based on the
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Himax HX8394 controller, such as the HannStar HSD060BHW4
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720x1440 TFT LCD panel that uses a MIPI-DSI interface.
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If M is selected the module will be called panel-himax-hx8394.
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config DRM_PANEL_ILITEK_IL9322
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tristate "Ilitek ILI9322 320x240 QVGA panels"
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depends on OF && SPI
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@ -13,6 +13,7 @@ obj-$(CONFIG_DRM_PANEL_EBBG_FT8719) += panel-ebbg-ft8719.o
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obj-$(CONFIG_DRM_PANEL_ELIDA_KD35T133) += panel-elida-kd35t133.o
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obj-$(CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02) += panel-feixin-k101-im2ba02.o
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obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) += panel-feiyang-fy07024di26a30d.o
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obj-$(CONFIG_DRM_PANEL_HIMAX_HX8394) += panel-himax-hx8394.o
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obj-$(CONFIG_DRM_PANEL_ILITEK_IL9322) += panel-ilitek-ili9322.o
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obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9341) += panel-ilitek-ili9341.o
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obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9881C) += panel-ilitek-ili9881c.o
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@ -0,0 +1,451 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for panels based on Himax HX8394 controller, such as:
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*
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* - HannStar HSD060BHW4 5.99" MIPI-DSI panel
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*
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* Copyright (C) 2021 Kamil Trzciński
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*
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* Based on drivers/gpu/drm/panel/panel-sitronix-st7703.c
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* Copyright (C) Purism SPC 2019
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*/
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/media-bus-format.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/regulator/consumer.h>
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#include <video/mipi_display.h>
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#include <drm/drm_mipi_dsi.h>
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#include <drm/drm_modes.h>
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#include <drm/drm_panel.h>
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#define DRV_NAME "panel-himax-hx8394"
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/* Manufacturer specific commands sent via DSI, listed in HX8394-F datasheet */
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#define HX8394_CMD_SETSEQUENCE 0xb0
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#define HX8394_CMD_SETPOWER 0xb1
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#define HX8394_CMD_SETDISP 0xb2
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#define HX8394_CMD_SETCYC 0xb4
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#define HX8394_CMD_SETVCOM 0xb6
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#define HX8394_CMD_SETTE 0xb7
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#define HX8394_CMD_SETSENSOR 0xb8
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#define HX8394_CMD_SETEXTC 0xb9
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#define HX8394_CMD_SETMIPI 0xba
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#define HX8394_CMD_SETOTP 0xbb
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#define HX8394_CMD_SETREGBANK 0xbd
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#define HX8394_CMD_UNKNOWN1 0xc0
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#define HX8394_CMD_SETDGCLUT 0xc1
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#define HX8394_CMD_SETID 0xc3
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#define HX8394_CMD_SETDDB 0xc4
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#define HX8394_CMD_UNKNOWN2 0xc6
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#define HX8394_CMD_SETCABC 0xc9
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#define HX8394_CMD_SETCABCGAIN 0xca
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#define HX8394_CMD_SETPANEL 0xcc
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#define HX8394_CMD_SETOFFSET 0xd2
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#define HX8394_CMD_SETGIP0 0xd3
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#define HX8394_CMD_UNKNOWN3 0xd4
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#define HX8394_CMD_SETGIP1 0xd5
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#define HX8394_CMD_SETGIP2 0xd6
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#define HX8394_CMD_SETGPO 0xd6
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#define HX8394_CMD_SETSCALING 0xdd
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#define HX8394_CMD_SETIDLE 0xdf
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#define HX8394_CMD_SETGAMMA 0xe0
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#define HX8394_CMD_SETCHEMODE_DYN 0xe4
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#define HX8394_CMD_SETCHE 0xe5
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#define HX8394_CMD_SETCESEL 0xe6
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#define HX8394_CMD_SET_SP_CMD 0xe9
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#define HX8394_CMD_SETREADINDEX 0xfe
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#define HX8394_CMD_GETSPIREAD 0xff
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struct hx8394 {
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struct device *dev;
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struct drm_panel panel;
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struct gpio_desc *reset_gpio;
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struct regulator *vcc;
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struct regulator *iovcc;
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bool prepared;
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const struct hx8394_panel_desc *desc;
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};
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struct hx8394_panel_desc {
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const struct drm_display_mode *mode;
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unsigned int lanes;
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unsigned long mode_flags;
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enum mipi_dsi_pixel_format format;
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int (*init_sequence)(struct hx8394 *ctx);
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};
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static inline struct hx8394 *panel_to_hx8394(struct drm_panel *panel)
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{
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return container_of(panel, struct hx8394, panel);
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}
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static int hsd060bhw4_init_sequence(struct hx8394 *ctx)
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{
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struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
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/* 5.19.8 SETEXTC: Set extension command (B9h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETEXTC,
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0xff, 0x83, 0x94);
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/* 5.19.2 SETPOWER: Set power (B1h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER,
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0x48, 0x11, 0x71, 0x09, 0x32, 0x24, 0x71, 0x31, 0x55, 0x30);
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/* 5.19.9 SETMIPI: Set MIPI control (BAh) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETMIPI,
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0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0);
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/* 5.19.3 SETDISP: Set display related register (B2h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETDISP,
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0x00, 0x80, 0x78, 0x0c, 0x07);
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/* 5.19.4 SETCYC: Set display waveform cycles (B4h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETCYC,
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0x12, 0x63, 0x12, 0x63, 0x12, 0x63, 0x01, 0x0c, 0x7c, 0x55,
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0x00, 0x3f, 0x12, 0x6b, 0x12, 0x6b, 0x12, 0x6b, 0x01, 0x0c,
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0x7c);
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/* 5.19.19 SETGIP0: Set GIP Option0 (D3h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP0,
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0x00, 0x00, 0x00, 0x00, 0x3c, 0x1c, 0x00, 0x00, 0x32, 0x10,
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0x09, 0x00, 0x09, 0x32, 0x15, 0xad, 0x05, 0xad, 0x32, 0x00,
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0x00, 0x00, 0x00, 0x37, 0x03, 0x0b, 0x0b, 0x37, 0x00, 0x00,
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0x00, 0x0c, 0x40);
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/* 5.19.20 Set GIP Option1 (D5h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP1,
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0x19, 0x19, 0x18, 0x18, 0x1b, 0x1b, 0x1a, 0x1a, 0x00, 0x01,
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0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x20, 0x21, 0x18, 0x18,
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0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
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0x24, 0x25, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
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0x18, 0x18, 0x18, 0x18, 0x18, 0x18);
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/* 5.19.21 Set GIP Option2 (D6h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP2,
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0x18, 0x18, 0x19, 0x19, 0x1b, 0x1b, 0x1a, 0x1a, 0x07, 0x06,
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0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x25, 0x24, 0x18, 0x18,
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0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
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0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
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0x18, 0x18, 0x18, 0x18, 0x18, 0x18);
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/* 5.19.25 SETGAMMA: Set gamma curve related setting (E0h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGAMMA,
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0x00, 0x04, 0x0c, 0x12, 0x14, 0x18, 0x1a, 0x18, 0x31, 0x3f,
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0x4d, 0x4c, 0x54, 0x65, 0x6b, 0x70, 0x7f, 0x82, 0x7e, 0x8a,
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0x99, 0x4a, 0x48, 0x49, 0x4b, 0x4a, 0x4c, 0x4b, 0x7f, 0x00,
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0x04, 0x0c, 0x11, 0x13, 0x17, 0x1a, 0x18, 0x31,
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0x3f, 0x4d, 0x4c, 0x54, 0x65, 0x6b, 0x70, 0x7f,
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0x82, 0x7e, 0x8a, 0x99, 0x4a, 0x48, 0x49, 0x4b,
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0x4a, 0x4c, 0x4b, 0x7f);
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/* 5.19.17 SETPANEL (CCh) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPANEL,
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0x0b);
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/* Unknown command, not listed in the HX8394-F datasheet */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN1,
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0x1f, 0x31);
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/* 5.19.5 SETVCOM: Set VCOM voltage (B6h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETVCOM,
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0x7d, 0x7d);
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/* Unknown command, not listed in the HX8394-F datasheet */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN3,
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0x02);
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/* 5.19.11 Set register bank (BDh) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
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0x01);
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/* 5.19.2 SETPOWER: Set power (B1h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER,
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0x00);
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/* 5.19.11 Set register bank (BDh) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
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0x00);
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/* Unknown command, not listed in the HX8394-F datasheet */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN3,
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0xed);
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return 0;
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}
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static const struct drm_display_mode hsd060bhw4_mode = {
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.hdisplay = 720,
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.hsync_start = 720 + 40,
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.hsync_end = 720 + 40 + 46,
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.htotal = 720 + 40 + 46 + 40,
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.vdisplay = 1440,
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.vsync_start = 1440 + 9,
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.vsync_end = 1440 + 9 + 7,
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.vtotal = 1440 + 9 + 7 + 7,
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.clock = 74250,
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.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
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.width_mm = 68,
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.height_mm = 136,
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};
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static const struct hx8394_panel_desc hsd060bhw4_desc = {
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.mode = &hsd060bhw4_mode,
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.lanes = 4,
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.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST,
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.format = MIPI_DSI_FMT_RGB888,
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.init_sequence = hsd060bhw4_init_sequence,
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};
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static int hx8394_enable(struct drm_panel *panel)
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{
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struct hx8394 *ctx = panel_to_hx8394(panel);
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struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
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int ret;
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ret = ctx->desc->init_sequence(ctx);
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if (ret) {
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dev_err(ctx->dev, "Panel init sequence failed: %d\n", ret);
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return ret;
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}
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ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
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if (ret) {
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dev_err(ctx->dev, "Failed to exit sleep mode: %d\n", ret);
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return ret;
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}
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/* Panel is operational 120 msec after reset */
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msleep(120);
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ret = mipi_dsi_dcs_set_display_on(dsi);
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if (ret) {
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dev_err(ctx->dev, "Failed to turn on the display: %d\n", ret);
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goto sleep_in;
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}
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return 0;
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sleep_in:
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/* This will probably fail, but let's try orderly power off anyway. */
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ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
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if (!ret)
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msleep(50);
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return ret;
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}
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static int hx8394_disable(struct drm_panel *panel)
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{
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struct hx8394 *ctx = panel_to_hx8394(panel);
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struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
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int ret;
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ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
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if (ret) {
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dev_err(ctx->dev, "Failed to enter sleep mode: %d\n", ret);
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return ret;
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}
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msleep(50); /* about 3 frames */
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return 0;
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}
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static int hx8394_unprepare(struct drm_panel *panel)
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{
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struct hx8394 *ctx = panel_to_hx8394(panel);
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if (!ctx->prepared)
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return 0;
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gpiod_set_value_cansleep(ctx->reset_gpio, 1);
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regulator_disable(ctx->iovcc);
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regulator_disable(ctx->vcc);
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ctx->prepared = false;
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return 0;
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}
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static int hx8394_prepare(struct drm_panel *panel)
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{
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struct hx8394 *ctx = panel_to_hx8394(panel);
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int ret;
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if (ctx->prepared)
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return 0;
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gpiod_set_value_cansleep(ctx->reset_gpio, 1);
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ret = regulator_enable(ctx->vcc);
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if (ret) {
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dev_err(ctx->dev, "Failed to enable vcc supply: %d\n", ret);
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return ret;
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}
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ret = regulator_enable(ctx->iovcc);
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if (ret) {
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dev_err(ctx->dev, "Failed to enable iovcc supply: %d\n", ret);
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goto disable_vcc;
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}
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gpiod_set_value_cansleep(ctx->reset_gpio, 0);
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msleep(180);
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ctx->prepared = true;
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return 0;
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disable_vcc:
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gpiod_set_value_cansleep(ctx->reset_gpio, 1);
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regulator_disable(ctx->vcc);
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return ret;
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}
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static int hx8394_get_modes(struct drm_panel *panel,
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struct drm_connector *connector)
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{
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struct hx8394 *ctx = panel_to_hx8394(panel);
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struct drm_display_mode *mode;
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mode = drm_mode_duplicate(connector->dev, ctx->desc->mode);
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if (!mode) {
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dev_err(ctx->dev, "Failed to add mode %ux%u@%u\n",
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ctx->desc->mode->hdisplay, ctx->desc->mode->vdisplay,
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drm_mode_vrefresh(ctx->desc->mode));
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return -ENOMEM;
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}
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drm_mode_set_name(mode);
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mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
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connector->display_info.width_mm = mode->width_mm;
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connector->display_info.height_mm = mode->height_mm;
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drm_mode_probed_add(connector, mode);
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return 1;
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}
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static const struct drm_panel_funcs hx8394_drm_funcs = {
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.disable = hx8394_disable,
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.unprepare = hx8394_unprepare,
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.prepare = hx8394_prepare,
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.enable = hx8394_enable,
|
||||
.get_modes = hx8394_get_modes,
|
||||
};
|
||||
|
||||
static int hx8394_probe(struct mipi_dsi_device *dsi)
|
||||
{
|
||||
struct device *dev = &dsi->dev;
|
||||
struct hx8394 *ctx;
|
||||
int ret;
|
||||
|
||||
ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
|
||||
if (!ctx)
|
||||
return -ENOMEM;
|
||||
|
||||
ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
|
||||
if (IS_ERR(ctx->reset_gpio))
|
||||
return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio),
|
||||
"Failed to get reset gpio\n");
|
||||
|
||||
mipi_dsi_set_drvdata(dsi, ctx);
|
||||
|
||||
ctx->dev = dev;
|
||||
ctx->desc = of_device_get_match_data(dev);
|
||||
|
||||
dsi->mode_flags = ctx->desc->mode_flags;
|
||||
dsi->format = ctx->desc->format;
|
||||
dsi->lanes = ctx->desc->lanes;
|
||||
|
||||
ctx->vcc = devm_regulator_get(dev, "vcc");
|
||||
if (IS_ERR(ctx->vcc))
|
||||
return dev_err_probe(dev, PTR_ERR(ctx->vcc),
|
||||
"Failed to request vcc regulator\n");
|
||||
|
||||
ctx->iovcc = devm_regulator_get(dev, "iovcc");
|
||||
if (IS_ERR(ctx->iovcc))
|
||||
return dev_err_probe(dev, PTR_ERR(ctx->iovcc),
|
||||
"Failed to request iovcc regulator\n");
|
||||
|
||||
drm_panel_init(&ctx->panel, dev, &hx8394_drm_funcs,
|
||||
DRM_MODE_CONNECTOR_DSI);
|
||||
|
||||
ret = drm_panel_of_backlight(&ctx->panel);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
drm_panel_add(&ctx->panel);
|
||||
|
||||
ret = mipi_dsi_attach(dsi);
|
||||
if (ret < 0) {
|
||||
dev_err_probe(dev, ret, "mipi_dsi_attach failed\n");
|
||||
drm_panel_remove(&ctx->panel);
|
||||
return ret;
|
||||
}
|
||||
|
||||
dev_dbg(dev, "%ux%u@%u %ubpp dsi %udl - ready\n",
|
||||
ctx->desc->mode->hdisplay, ctx->desc->mode->vdisplay,
|
||||
drm_mode_vrefresh(ctx->desc->mode),
|
||||
mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void hx8394_shutdown(struct mipi_dsi_device *dsi)
|
||||
{
|
||||
struct hx8394 *ctx = mipi_dsi_get_drvdata(dsi);
|
||||
int ret;
|
||||
|
||||
ret = drm_panel_disable(&ctx->panel);
|
||||
if (ret < 0)
|
||||
dev_err(&dsi->dev, "Failed to disable panel: %d\n", ret);
|
||||
|
||||
ret = drm_panel_unprepare(&ctx->panel);
|
||||
if (ret < 0)
|
||||
dev_err(&dsi->dev, "Failed to unprepare panel: %d\n", ret);
|
||||
}
|
||||
|
||||
static void hx8394_remove(struct mipi_dsi_device *dsi)
|
||||
{
|
||||
struct hx8394 *ctx = mipi_dsi_get_drvdata(dsi);
|
||||
int ret;
|
||||
|
||||
hx8394_shutdown(dsi);
|
||||
|
||||
ret = mipi_dsi_detach(dsi);
|
||||
if (ret < 0)
|
||||
dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret);
|
||||
|
||||
drm_panel_remove(&ctx->panel);
|
||||
}
|
||||
|
||||
static const struct of_device_id hx8394_of_match[] = {
|
||||
{ .compatible = "hannstar,hsd060bhw4", .data = &hsd060bhw4_desc },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, hx8394_of_match);
|
||||
|
||||
static struct mipi_dsi_driver hx8394_driver = {
|
||||
.probe = hx8394_probe,
|
||||
.remove = hx8394_remove,
|
||||
.shutdown = hx8394_shutdown,
|
||||
.driver = {
|
||||
.name = DRV_NAME,
|
||||
.of_match_table = hx8394_of_match,
|
||||
},
|
||||
};
|
||||
module_mipi_dsi_driver(hx8394_driver);
|
||||
|
||||
MODULE_AUTHOR("Kamil Trzciński <ayufan@ayufan.eu>");
|
||||
MODULE_DESCRIPTION("DRM driver for Himax HX8394 based MIPI DSI panels");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue