i40e: Persistent LLDP support
This patch adds a function to read NVM module data and uses it to read current LLDP agent configuration from NVM API version 1.8. Signed-off-by: Sylwia Wnuczko <sylwia.wnuczko@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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@ -877,7 +877,23 @@ i40e_status i40e_init_dcb(struct i40e_hw *hw, bool enable_mib_change)
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return I40E_NOT_SUPPORTED;
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/* Read LLDP NVM area */
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ret = i40e_read_lldp_cfg(hw, &lldp_cfg);
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if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT) {
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u8 offset = 0;
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if (hw->mac.type == I40E_MAC_XL710)
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offset = I40E_LLDP_CURRENT_STATUS_XL710_OFFSET;
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else if (hw->mac.type == I40E_MAC_X722)
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offset = I40E_LLDP_CURRENT_STATUS_X722_OFFSET;
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else
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return I40E_NOT_SUPPORTED;
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ret = i40e_read_nvm_module_data(hw,
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I40E_SR_EMP_SR_SETTINGS_PTR,
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offset, 1,
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&lldp_cfg.adminstatus);
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} else {
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ret = i40e_read_lldp_cfg(hw, &lldp_cfg);
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}
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if (ret)
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return I40E_ERR_NOT_READY;
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@ -30,6 +30,8 @@
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#define I40E_CEE_SUBTYPE_APP_PRI 4
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#define I40E_CEE_MAX_FEAT_TYPE 3
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#define I40E_LLDP_CURRENT_STATUS_XL710_OFFSET 0x2B
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#define I40E_LLDP_CURRENT_STATUS_X722_OFFSET 0x31
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/* Defines for LLDP TLV header */
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#define I40E_LLDP_TLV_LEN_SHIFT 0
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#define I40E_LLDP_TLV_LEN_MASK (0x01FF << I40E_LLDP_TLV_LEN_SHIFT)
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@ -321,6 +321,77 @@ i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
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return ret_code;
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}
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/**
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* i40e_read_nvm_module_data - Reads NVM Buffer to specified memory location
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* @hw: pointer to the HW structure
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* @module_ptr: Pointer to module in words with respect to NVM beginning
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* @offset: offset in words from module start
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* @words_data_size: Words to read from NVM
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* @data_ptr: Pointer to memory location where resulting buffer will be stored
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**/
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i40e_status i40e_read_nvm_module_data(struct i40e_hw *hw,
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u8 module_ptr, u16 offset,
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u16 words_data_size,
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u16 *data_ptr)
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{
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i40e_status status;
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u16 ptr_value = 0;
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u32 flat_offset;
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if (module_ptr != 0) {
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status = i40e_read_nvm_word(hw, module_ptr, &ptr_value);
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if (status) {
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i40e_debug(hw, I40E_DEBUG_ALL,
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"Reading nvm word failed.Error code: %d.\n",
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status);
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return I40E_ERR_NVM;
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}
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}
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#define I40E_NVM_INVALID_PTR_VAL 0x7FFF
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#define I40E_NVM_INVALID_VAL 0xFFFF
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/* Pointer not initialized */
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if (ptr_value == I40E_NVM_INVALID_PTR_VAL ||
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ptr_value == I40E_NVM_INVALID_VAL)
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return I40E_ERR_BAD_PTR;
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/* Check whether the module is in SR mapped area or outside */
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if (ptr_value & I40E_PTR_TYPE) {
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/* Pointer points outside of the Shared RAM mapped area */
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ptr_value &= ~I40E_PTR_TYPE;
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/* PtrValue in 4kB units, need to convert to words */
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ptr_value /= 2;
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flat_offset = ((u32)ptr_value * 0x1000) + (u32)offset;
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status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
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if (!status) {
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status = i40e_aq_read_nvm(hw, 0, 2 * flat_offset,
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2 * words_data_size,
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data_ptr, true, NULL);
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i40e_release_nvm(hw);
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if (status) {
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i40e_debug(hw, I40E_DEBUG_ALL,
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"Reading nvm aq failed.Error code: %d.\n",
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status);
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return I40E_ERR_NVM;
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}
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} else {
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return I40E_ERR_NVM;
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}
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} else {
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/* Read from the Shadow RAM */
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status = i40e_read_nvm_buffer(hw, ptr_value + offset,
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&words_data_size, data_ptr);
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if (status) {
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i40e_debug(hw, I40E_DEBUG_ALL,
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"Reading nvm buffer failed.Error code: %d.\n",
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status);
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}
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}
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return status;
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}
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/**
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* i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register
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* @hw: pointer to the HW structure
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@ -429,6 +500,36 @@ static i40e_status __i40e_read_nvm_buffer(struct i40e_hw *hw,
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return i40e_read_nvm_buffer_srctl(hw, offset, words, data);
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}
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/**
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* i40e_read_nvm_buffer - Reads Shadow RAM buffer and acquire lock if necessary
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* @hw: pointer to the HW structure
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* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
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* @words: (in) number of words to read; (out) number of words actually read
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* @data: words read from the Shadow RAM
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*
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* Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
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* method. The buffer read is preceded by the NVM ownership take
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* and followed by the release.
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**/
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i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
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u16 *words, u16 *data)
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{
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i40e_status ret_code = 0;
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if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) {
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ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
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if (!ret_code) {
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ret_code = i40e_read_nvm_buffer_aq(hw, offset, words,
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data);
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i40e_release_nvm(hw);
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}
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} else {
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ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data);
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}
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return ret_code;
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}
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/**
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* i40e_write_nvm_aq - Writes Shadow RAM.
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* @hw: pointer to the HW structure.
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@ -315,6 +315,12 @@ i40e_status i40e_acquire_nvm(struct i40e_hw *hw,
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void i40e_release_nvm(struct i40e_hw *hw);
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i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
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u16 *data);
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i40e_status i40e_read_nvm_module_data(struct i40e_hw *hw,
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u8 module_ptr, u16 offset,
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u16 words_data_size,
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u16 *data_ptr);
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i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
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u16 *words, u16 *data);
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i40e_status i40e_update_nvm_checksum(struct i40e_hw *hw);
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i40e_status i40e_validate_nvm_checksum(struct i40e_hw *hw,
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u16 *checksum);
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@ -1318,6 +1318,7 @@ struct i40e_hw_port_stats {
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#define I40E_SR_VPD_PTR 0x2F
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#define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
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#define I40E_SR_SW_CHECKSUM_WORD 0x3F
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#define I40E_SR_EMP_SR_SETTINGS_PTR 0x48
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/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
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#define I40E_SR_VPD_MODULE_MAX_SIZE 1024
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