From 16615a4c6f4d54d7655dff19e7061c76043f907d Mon Sep 17 00:00:00 2001 From: Iyappan Subramanian Date: Mon, 26 Oct 2015 15:25:15 -0700 Subject: [PATCH 1/2] drivers: net: xgene: Add support RGMII TX/RX delay configuration Add RGMII TX/RX delay configuration support. RGMII standard requires 2ns delay to help the RGMII bridge receiver to sample data correctly. If the default value does not provide proper centering of the data sample, the TX/RX delay parameters can be used to adjust accordingly. Signed-off-by: Iyappan Subramanian Signed-off-by: David S. Miller --- .../net/ethernet/apm/xgene/xgene_enet_hw.c | 8 ++- .../net/ethernet/apm/xgene/xgene_enet_hw.h | 1 + .../net/ethernet/apm/xgene/xgene_enet_main.c | 49 +++++++++++++++++++ .../net/ethernet/apm/xgene/xgene_enet_main.h | 2 + 4 files changed, 59 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.c b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.c index 652f21889a48..33850a0f7e82 100644 --- a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.c +++ b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.c @@ -461,6 +461,7 @@ static void xgene_gmac_reset(struct xgene_enet_pdata *pdata) static void xgene_gmac_init(struct xgene_enet_pdata *pdata) { + struct device *dev = &pdata->pdev->dev; u32 value, mc2; u32 intf_ctl, rgmii; u32 icm0, icm2; @@ -490,7 +491,12 @@ static void xgene_gmac_init(struct xgene_enet_pdata *pdata) default: ENET_INTERFACE_MODE2_SET(&mc2, 2); intf_ctl |= ENET_GHD_MODE; - CFG_TXCLK_MUXSEL0_SET(&rgmii, 4); + + if (dev->of_node) { + CFG_TXCLK_MUXSEL0_SET(&rgmii, pdata->tx_delay); + CFG_RXCLK_MUXSEL0_SET(&rgmii, pdata->rx_delay); + } + xgene_enet_rd_csr(pdata, DEBUG_REG_ADDR, &value); value |= CFG_BYPASS_UNISEC_TX | CFG_BYPASS_UNISEC_RX; xgene_enet_wr_csr(pdata, DEBUG_REG_ADDR, value); diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h index ff05bbcff26d..6dee73c3c1e1 100644 --- a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h +++ b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h @@ -144,6 +144,7 @@ enum xgene_enet_rm { #define CFG_BYPASS_UNISEC_RX BIT(1) #define CFG_CLE_BYPASS_EN0 BIT(31) #define CFG_TXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 29, 3) +#define CFG_RXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 26, 3) #define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2) #define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12) diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_main.c b/drivers/net/ethernet/apm/xgene/xgene_enet_main.c index 6b1846df7b0c..ce1068771b32 100644 --- a/drivers/net/ethernet/apm/xgene/xgene_enet_main.c +++ b/drivers/net/ethernet/apm/xgene/xgene_enet_main.c @@ -1118,6 +1118,47 @@ static int xgene_get_port_id_dt(struct device *dev, struct xgene_enet_pdata *pda return ret; } +static int xgene_get_tx_delay(struct xgene_enet_pdata *pdata) +{ + struct device *dev = &pdata->pdev->dev; + int delay, ret; + + ret = of_property_read_u32(dev->of_node, "tx-delay", &delay); + if (ret) { + pdata->tx_delay = 4; + return 0; + } + + if (delay < 0 || delay > 7) { + dev_err(dev, "Invalid tx-delay specified\n"); + return -EINVAL; + } + + pdata->tx_delay = delay; + + return 0; +} + +static int xgene_get_rx_delay(struct xgene_enet_pdata *pdata) +{ + struct device *dev = &pdata->pdev->dev; + int delay, ret; + + ret = of_property_read_u32(dev->of_node, "rx-delay", &delay); + if (ret) { + pdata->rx_delay = 2; + return 0; + } + + if (delay < 0 || delay > 7) { + dev_err(dev, "Invalid rx-delay specified\n"); + return -EINVAL; + } + + pdata->rx_delay = delay; + + return 0; +} static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata) { @@ -1194,6 +1235,14 @@ static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata) return -ENODEV; } + ret = xgene_get_tx_delay(pdata); + if (ret) + return ret; + + ret = xgene_get_rx_delay(pdata); + if (ret) + return ret; + ret = platform_get_irq(pdev, 0); if (ret <= 0) { dev_err(dev, "Unable to get ENET Rx IRQ\n"); diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_main.h b/drivers/net/ethernet/apm/xgene/xgene_enet_main.h index ff89a5d98d01..a6e56b88c0a0 100644 --- a/drivers/net/ethernet/apm/xgene/xgene_enet_main.h +++ b/drivers/net/ethernet/apm/xgene/xgene_enet_main.h @@ -184,6 +184,8 @@ struct xgene_enet_pdata { u8 bp_bufnum; u16 ring_num; u32 mss; + u8 tx_delay; + u8 rx_delay; }; struct xgene_indirect_ctl { From 6ccbe6b248ef8cc31477a388ea9841b56030bea9 Mon Sep 17 00:00:00 2001 From: Iyappan Subramanian Date: Mon, 26 Oct 2015 15:25:16 -0700 Subject: [PATCH 2/2] Documentation: dts: xgene: Add TX/RX delay field Signed-off-by: Iyappan Subramanian Signed-off-by: David S. Miller --- .../devicetree/bindings/net/apm-xgene-enet.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/net/apm-xgene-enet.txt b/Documentation/devicetree/bindings/net/apm-xgene-enet.txt index f55aa280d34f..078060a97f95 100644 --- a/Documentation/devicetree/bindings/net/apm-xgene-enet.txt +++ b/Documentation/devicetree/bindings/net/apm-xgene-enet.txt @@ -37,6 +37,14 @@ Required properties for ethernet interfaces that have external PHY: Optional properties: - status: Should be "ok" or "disabled" for enabled/disabled. Default is "ok". +- tx-delay: Delay value for RGMII bridge TX clock. + Valid values are between 0 to 7, that maps to + 417, 717, 1020, 1321, 1611, 1913, 2215, 2514 ps + Default value is 4, which corresponds to 1611 ps +- rx-delay: Delay value for RGMII bridge RX clock. + Valid values are between 0 to 7, that maps to + 273, 589, 899, 1222, 1480, 1806, 2147, 2464 ps + Default value is 2, which corresponds to 899 ps Example: menetclk: menetclk { @@ -72,5 +80,7 @@ Example: /* Board-specific peripheral configurations */ &menet { + tx-delay = <4>; + rx-delay = <2>; status = "ok"; };