From 65bb9dd0ec7966880b68b252b9a71585f0b539e8 Mon Sep 17 00:00:00 2001 From: Anshuman Gupta Date: Fri, 17 Apr 2020 22:58:35 +0530 Subject: [PATCH] drm/i915: Add ICL PG3 PW ID for EHL Gen11 onwards PG3 contains functions for pipe B, external displays, and VGA. Add missing ICL_DISP_PW_3 for ehl_power_wells. Cc: Animesh Manna Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1737 Signed-off-by: Anshuman Gupta Acked-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20200417172835.15461-1-anshuman.gupta@intel.com --- drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index f72b8ed095ca..fa46ea6c6e01 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -3902,7 +3902,7 @@ static const struct i915_power_well_desc ehl_power_wells[] = { .name = "power well 3", .domains = ICL_PW_3_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = DISP_PW_ID_NONE, + .id = ICL_DISP_PW_3, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = ICL_PW_CTL_IDX_PW_3,