mtd: nand: omap2: handle nand on gpmc
GPMC platform initialization has been modified to fill NAND platform data with GPMC NAND register details. As these registers are accessible in NAND driver itself, configure NAND in GPMC by itself. Modified prefetch and ecc functions are logically same as the corresponding exported symbols from GPMC code. Note: Verfying that other CS have not yet enabled for prefetch & ecc has to be incorporated. Currently this causes no issues as there are no boards that use NAND on multiple CS. With ongoing GPMC driver migration, perhaps it would be better to consider NAND connected on multiple CS as a single peripheral using multiple CS. This would make handling multiple CS issues easier. Signed-off-by: Afzal Mohammed <afzal@ti.com> Acked-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Afzal Mohammed
Tony Lindgren
parent
d126d0158b
commit
65b97cf6b8
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@ -101,6 +101,16 @@
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#define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
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#define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
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#define PREFETCH_CONFIG1_CS_SHIFT 24
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#define ECC_CONFIG_CS_SHIFT 1
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#define CS_MASK 0x7
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#define ENABLE_PREFETCH (0x1 << 7)
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#define DMA_MPU_MODE_SHIFT 2
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#define ECCSIZE1_SHIFT 22
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#define ECC1RESULTSIZE 0x1
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#define ECCCLEAR 0x100
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#define ECC1 0x1
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/* oob info generated runtime depending on ecc algorithm and layout selected */
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static struct nand_ecclayout omap_oobinfo;
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/* Define some generic bad / good block scan pattern which are used
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@ -133,6 +143,7 @@ struct omap_nand_info {
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} iomode;
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u_char *buf;
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int buf_len;
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struct gpmc_nand_regs reg;
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#ifdef CONFIG_MTD_NAND_OMAP_BCH
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struct bch_control *bch;
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@ -140,6 +151,63 @@ struct omap_nand_info {
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#endif
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};
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/**
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* omap_prefetch_enable - configures and starts prefetch transfer
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* @cs: cs (chip select) number
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* @fifo_th: fifo threshold to be used for read/ write
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* @dma_mode: dma mode enable (1) or disable (0)
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* @u32_count: number of bytes to be transferred
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* @is_write: prefetch read(0) or write post(1) mode
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*/
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static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode,
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unsigned int u32_count, int is_write, struct omap_nand_info *info)
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{
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u32 val;
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if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
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return -1;
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if (readl(info->reg.gpmc_prefetch_control))
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return -EBUSY;
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/* Set the amount of bytes to be prefetched */
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writel(u32_count, info->reg.gpmc_prefetch_config2);
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/* Set dma/mpu mode, the prefetch read / post write and
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* enable the engine. Set which cs is has requested for.
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*/
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val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) |
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PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH |
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(dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write));
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writel(val, info->reg.gpmc_prefetch_config1);
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/* Start the prefetch engine */
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writel(0x1, info->reg.gpmc_prefetch_control);
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return 0;
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}
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/**
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* omap_prefetch_reset - disables and stops the prefetch engine
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*/
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static int omap_prefetch_reset(int cs, struct omap_nand_info *info)
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{
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u32 config1;
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/* check if the same module/cs is trying to reset */
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config1 = readl(info->reg.gpmc_prefetch_config1);
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if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs)
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return -EINVAL;
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/* Stop the PFPW engine */
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writel(0x0, info->reg.gpmc_prefetch_control);
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/* Reset/disable the PFPW engine */
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writel(0x0, info->reg.gpmc_prefetch_config1);
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return 0;
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}
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/**
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* omap_hwcontrol - hardware specific access to control-lines
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* @mtd: MTD device structure
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@ -158,13 +226,13 @@ static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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if (cmd != NAND_CMD_NONE) {
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if (ctrl & NAND_CLE)
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gpmc_nand_write(info->gpmc_cs, GPMC_NAND_COMMAND, cmd);
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writeb(cmd, info->reg.gpmc_nand_command);
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else if (ctrl & NAND_ALE)
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gpmc_nand_write(info->gpmc_cs, GPMC_NAND_ADDRESS, cmd);
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writeb(cmd, info->reg.gpmc_nand_address);
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else /* NAND_NCE */
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gpmc_nand_write(info->gpmc_cs, GPMC_NAND_DATA, cmd);
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writeb(cmd, info->reg.gpmc_nand_data);
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}
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}
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@ -198,7 +266,8 @@ static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
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iowrite8(*p++, info->nand.IO_ADDR_W);
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/* wait until buffer is available for write */
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do {
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status = gpmc_read_status(GPMC_STATUS_BUFFER);
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status = readl(info->reg.gpmc_status) &
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GPMC_STATUS_BUFF_EMPTY;
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} while (!status);
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}
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}
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@ -235,7 +304,8 @@ static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
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iowrite16(*p++, info->nand.IO_ADDR_W);
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/* wait until buffer is available for write */
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do {
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status = gpmc_read_status(GPMC_STATUS_BUFFER);
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status = readl(info->reg.gpmc_status) &
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GPMC_STATUS_BUFF_EMPTY;
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} while (!status);
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}
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}
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@ -265,8 +335,8 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
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}
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/* configure and start prefetch transfer */
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ret = gpmc_prefetch_enable(info->gpmc_cs,
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PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0);
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ret = omap_prefetch_enable(info->gpmc_cs,
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PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info);
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if (ret) {
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/* PFPW engine is busy, use cpu copy method */
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if (info->nand.options & NAND_BUSWIDTH_16)
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@ -275,14 +345,15 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
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omap_read_buf8(mtd, (u_char *)p, len);
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} else {
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do {
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r_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
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r_count = readl(info->reg.gpmc_prefetch_status);
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r_count = GPMC_PREFETCH_STATUS_FIFO_CNT(r_count);
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r_count = r_count >> 2;
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ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
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p += r_count;
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len -= r_count << 2;
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} while (len);
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/* disable and stop the PFPW engine */
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gpmc_prefetch_reset(info->gpmc_cs);
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omap_prefetch_reset(info->gpmc_cs, info);
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}
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}
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@ -301,6 +372,7 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
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int i = 0, ret = 0;
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u16 *p = (u16 *)buf;
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unsigned long tim, limit;
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u32 val;
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/* take care of subpage writes */
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if (len % 2 != 0) {
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@ -310,8 +382,8 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
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}
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/* configure and start prefetch transfer */
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ret = gpmc_prefetch_enable(info->gpmc_cs,
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PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1);
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ret = omap_prefetch_enable(info->gpmc_cs,
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PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info);
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if (ret) {
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/* PFPW engine is busy, use cpu copy method */
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if (info->nand.options & NAND_BUSWIDTH_16)
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@ -320,7 +392,8 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
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omap_write_buf8(mtd, (u_char *)p, len);
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} else {
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while (len) {
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w_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
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w_count = readl(info->reg.gpmc_prefetch_status);
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w_count = GPMC_PREFETCH_STATUS_FIFO_CNT(w_count);
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w_count = w_count >> 1;
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for (i = 0; (i < w_count) && len; i++, len -= 2)
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iowrite16(*p++, info->nand.IO_ADDR_W);
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@ -329,11 +402,14 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
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tim = 0;
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limit = (loops_per_jiffy *
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msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
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while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
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do {
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cpu_relax();
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val = readl(info->reg.gpmc_prefetch_status);
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val = GPMC_PREFETCH_STATUS_COUNT(val);
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} while (val && (tim++ < limit));
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/* disable and stop the PFPW engine */
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gpmc_prefetch_reset(info->gpmc_cs);
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omap_prefetch_reset(info->gpmc_cs, info);
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}
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}
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@ -365,6 +441,7 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
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unsigned long tim, limit;
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unsigned n;
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int ret;
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u32 val;
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if (addr >= high_memory) {
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struct page *p1;
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@ -396,9 +473,9 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
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tx->callback_param = &info->comp;
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dmaengine_submit(tx);
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/* configure and start prefetch transfer */
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ret = gpmc_prefetch_enable(info->gpmc_cs,
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PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write);
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/* configure and start prefetch transfer */
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ret = omap_prefetch_enable(info->gpmc_cs,
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PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info);
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if (ret)
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/* PFPW engine is busy, use cpu copy method */
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goto out_copy_unmap;
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@ -410,11 +487,15 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
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wait_for_completion(&info->comp);
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tim = 0;
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limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
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while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
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do {
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cpu_relax();
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val = readl(info->reg.gpmc_prefetch_status);
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val = GPMC_PREFETCH_STATUS_COUNT(val);
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} while (val && (tim++ < limit));
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/* disable and stop the PFPW engine */
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gpmc_prefetch_reset(info->gpmc_cs);
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omap_prefetch_reset(info->gpmc_cs, info);
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dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
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return 0;
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@ -474,7 +555,8 @@ static irqreturn_t omap_nand_irq(int this_irq, void *dev)
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u32 irq_stat;
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irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS);
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bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
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bytes = readl(info->reg.gpmc_prefetch_status);
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bytes = GPMC_PREFETCH_STATUS_FIFO_CNT(bytes);
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bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
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if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
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if (irq_stat & 0x2)
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@ -534,8 +616,8 @@ static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
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init_completion(&info->comp);
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/* configure and start prefetch transfer */
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ret = gpmc_prefetch_enable(info->gpmc_cs,
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PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0);
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ret = omap_prefetch_enable(info->gpmc_cs,
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PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info);
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if (ret)
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/* PFPW engine is busy, use cpu copy method */
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goto out_copy;
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@ -549,7 +631,7 @@ static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
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wait_for_completion(&info->comp);
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/* disable and stop the PFPW engine */
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gpmc_prefetch_reset(info->gpmc_cs);
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omap_prefetch_reset(info->gpmc_cs, info);
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return;
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out_copy:
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@ -572,6 +654,7 @@ static void omap_write_buf_irq_pref(struct mtd_info *mtd,
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struct omap_nand_info, mtd);
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int ret = 0;
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unsigned long tim, limit;
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u32 val;
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if (len <= mtd->oobsize) {
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omap_write_buf_pref(mtd, buf, len);
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@ -583,8 +666,8 @@ static void omap_write_buf_irq_pref(struct mtd_info *mtd,
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init_completion(&info->comp);
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/* configure and start prefetch transfer : size=24 */
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ret = gpmc_prefetch_enable(info->gpmc_cs,
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(PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1);
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ret = omap_prefetch_enable(info->gpmc_cs,
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(PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info);
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if (ret)
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/* PFPW engine is busy, use cpu copy method */
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goto out_copy;
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@ -599,11 +682,14 @@ static void omap_write_buf_irq_pref(struct mtd_info *mtd,
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/* wait for data to flushed-out before reset the prefetch */
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tim = 0;
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limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
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while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
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do {
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val = readl(info->reg.gpmc_prefetch_status);
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val = GPMC_PREFETCH_STATUS_COUNT(val);
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cpu_relax();
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} while (val && (tim++ < limit));
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/* disable and stop the PFPW engine */
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gpmc_prefetch_reset(info->gpmc_cs);
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omap_prefetch_reset(info->gpmc_cs, info);
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return;
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out_copy:
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@ -843,7 +929,20 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
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{
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struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
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mtd);
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return gpmc_calculate_ecc(info->gpmc_cs, dat, ecc_code);
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u32 val;
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val = readl(info->reg.gpmc_ecc_config);
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if (((val >> ECC_CONFIG_CS_SHIFT) & ~CS_MASK) != info->gpmc_cs)
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return -EINVAL;
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/* read ecc result */
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val = readl(info->reg.gpmc_ecc1_result);
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*ecc_code++ = val; /* P128e, ..., P1e */
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*ecc_code++ = val >> 16; /* P128o, ..., P1o */
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/* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
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*ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
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return 0;
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}
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/**
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@ -857,8 +956,34 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
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mtd);
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struct nand_chip *chip = mtd->priv;
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unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
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u32 val;
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gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size);
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/* clear ecc and enable bits */
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val = ECCCLEAR | ECC1;
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writel(val, info->reg.gpmc_ecc_control);
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/* program ecc and result sizes */
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val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
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ECC1RESULTSIZE);
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writel(val, info->reg.gpmc_ecc_size_config);
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switch (mode) {
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case NAND_ECC_READ:
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case NAND_ECC_WRITE:
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writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
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break;
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case NAND_ECC_READSYN:
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writel(ECCCLEAR, info->reg.gpmc_ecc_control);
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break;
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default:
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dev_info(&info->pdev->dev,
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"error: unrecognized Mode[%d]!\n", mode);
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break;
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}
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/* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
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val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
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writel(val, info->reg.gpmc_ecc_config);
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}
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/**
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@ -886,10 +1011,9 @@ static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
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else
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timeo += (HZ * 20) / 1000;
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gpmc_nand_write(info->gpmc_cs,
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GPMC_NAND_COMMAND, (NAND_CMD_STATUS & 0xFF));
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writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
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while (time_before(jiffies, timeo)) {
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status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA);
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status = readb(info->reg.gpmc_nand_data);
|
||||
if (status & NAND_STATUS_READY)
|
||||
break;
|
||||
cond_resched();
|
||||
|
|
@ -909,22 +1033,13 @@ static int omap_dev_ready(struct mtd_info *mtd)
|
|||
struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
|
||||
mtd);
|
||||
|
||||
val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
|
||||
if ((val & 0x100) == 0x100) {
|
||||
/* Clear IRQ Interrupt */
|
||||
val |= 0x100;
|
||||
val &= ~(0x0);
|
||||
gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, val);
|
||||
} else {
|
||||
unsigned int cnt = 0;
|
||||
while (cnt++ < 0x1FF) {
|
||||
if ((val & 0x100) == 0x100)
|
||||
return 0;
|
||||
val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
|
||||
}
|
||||
}
|
||||
val = readl(info->reg.gpmc_status);
|
||||
|
||||
return 1;
|
||||
if ((val & 0x100) == 0x100) {
|
||||
return 1;
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MTD_NAND_OMAP_BCH
|
||||
|
|
@ -1175,6 +1290,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
|
|||
|
||||
info->gpmc_cs = pdata->cs;
|
||||
info->phys_base = pdata->phys_base;
|
||||
info->reg = pdata->reg;
|
||||
|
||||
info->mtd.priv = &info->nand;
|
||||
info->mtd.name = dev_name(&pdev->dev);
|
||||
|
|
|
|||
Loading…
Reference in New Issue