Renesas ARM based SoC Board Updates for v3.15
* r8a7791 (R-Car M2) based Koelsch board - Fix error return code check from clk_get() - Add SATA0 support - Conditionally select MICREL_PHY for Multiplatform * r8a7790 (R-Car H2) based Lager board - Add USBHS support - Fix error return code check from clk_get() - Add SATA support - Make spi_flash_data const - Add VIN1 SoC camera support - Conditionally select CONFIG_MICREL_PHY * r8a7778 (R-Car M1) based Bock-W board - Add USB Func DMAEngine support - Use HPBIF DMAEngine for sound - Use SSI DMAEngine for sound * emev2 (Emma Mobile EV2) based kzm9d board - Use common clock framework * r8a773a0 (SH-Mobile AG5) based kzm9g board - Add zboot support * Many boards - Conditionally select SMSC_PHY -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJS8yASAAoJENfPZGlqN0++f1oQAK/Kw1GLxU6hKGDU57X2UgfR gx1HZm4vQFzBKF1d+Trpc/GRzWzMUbLvoA70GWfs7aoYrT0ZZaOHrOD5mWiet1Dh 2Mcrvja60yC5BP5mvmXsxWB0UK6TgNqlwI+6zoqFNE5yjY3a1FG3Upi6ARvhp2Td FnLInNvASiTGOmpY7RU8224L78u10VFiWOkektKmjIK2BWCBQ04oM4Y26Jg7Nedg Eu0KfIHAC/UFHjV4vb0/RRRBQC4nm4xgRr7ihIp347aFTTkzemhC5+PN4ebNMNIq u0ISWg89GcESXM126ft+7fLmzn8zM5V/FJkkKY01vpsGrSUJj7OQUDU8huhnaEav f2qYyxzcYzqLIekKIqBCqzqWJDH4AxQJTyK3L3sLzt1hWT4nWcVwlpiRUZ21X+H3 OLB9AsscFdkeLy4eTE2pgvAAxarj62e2ggcWG3DuoLap8sVW25a6+mN5IJqUxtGp Qyi6MqWuVBNMYDrZKgmy5HmoWItCvO03mwBSJOR8lPjz0FloAovEculzbtEWLVll LKwj3bM9wYBHa34f2CP01k24v4S+9zavV+mJK+6lOl/VJyay4Tk1p12oNhCNqzA9 0/0RS5ejaP2EvbKSp+pfsX30c2A+tuFps+ShEea1fBRbdcmIdT0M4+ELiLkwcZFp P5q453rEqQQj5HBplAXg =/cww -----END PGP SIGNATURE----- Merge tag 'renesas-boards-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/boards Merge "Renesas ARM based SoC Board Updates for v3.15" from Simon Horman: * r8a7791 (R-Car M2) based Koelsch board - Fix error return code check from clk_get() - Add SATA0 support - Conditionally select MICREL_PHY for Multiplatform * r8a7790 (R-Car H2) based Lager board - Add USBHS support - Fix error return code check from clk_get() - Add SATA support - Make spi_flash_data const - Add VIN1 SoC camera support - Conditionally select CONFIG_MICREL_PHY * r8a7778 (R-Car M1) based Bock-W board - Add USB Func DMAEngine support - Use HPBIF DMAEngine for sound - Use SSI DMAEngine for sound * emev2 (Emma Mobile EV2) based kzm9d board - Use common clock framework * r8a773a0 (SH-Mobile AG5) based kzm9g board - Add zboot support * Many boards - Conditionally select SMSC_PHY * tag 'renesas-boards-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (21 commits) ARM: shmobile: Remove Lager USBHS UDC ifdefs ARM: shmobile: lager: Add USBHS support ARM: shmobile: koelsch: fix error return code check from clk_get() ARM: shmobile: lager: fix error return code check from clk_get() ARM: shmobile: marzen: Conditionally select SMSC_PHY ARM: shmobile: mackerel: Conditionally select SMSC_PHY ARM: shmobile: kzm9d: Conditionally select SMSC_PHY ARM: shmobile: bockw: Sort Kconfig node's selections ARM: shmobile: armadillo800eva: Conditionally select SMSC_PHY ARM: shmobile: ape6evm: Conditionally select SMSC_PHY ARM: shmobile: koelsch: Add SATA0 support ARM: shmobile: lager: Add SATA support ARM: shmobile: lager: Make spi_flash_data const ARM: shmobile: kzm9d: Use common clock framework ARM: shmobile: lager: Add VIN1 SoC camera support ARM: mach-shmobile: kzm9g: add zboot support ARM: shmobile: koelsch: Conditionally select MICREL_PHY for Multiplatform ARM: shmobile: bockw: add USB Func DMAEngine support ARM: shmobile: bockw: use HPBIF DMAEngine for sound ARM: shmobile: bockw: use SSI DMAEngine for sound ... Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
65b108ecde
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@ -45,15 +45,18 @@ config MACH_GENMAI
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config MACH_KOELSCH
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bool "Koelsch board"
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depends on ARCH_R8A7791
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select MICREL_PHY if SH_ETH
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config MACH_KZM9D
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bool "KZM9D board"
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depends on ARCH_EMEV2
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select REGULATOR_FIXED_VOLTAGE if REGULATOR
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select SMSC_PHY if SMSC911X
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config MACH_LAGER
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bool "Lager board"
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depends on ARCH_R8A7790
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select MICREL_PHY if SH_ETH
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comment "Renesas ARM SoCs System Configuration"
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endif
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@ -154,11 +157,13 @@ comment "Renesas ARM SoCs Board Type"
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config MACH_APE6EVM
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bool "APE6EVM board"
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depends on ARCH_R8A73A4
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select SMSC_PHY if SMSC911X
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select USE_OF
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config MACH_APE6EVM_REFERENCE
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bool "APE6EVM board - Reference Device Tree Implementation"
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depends on ARCH_R8A73A4
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select SMSC_PHY if SMSC911X
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select USE_OF
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---help---
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Use reference implementation of APE6EVM board support
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@ -172,6 +177,7 @@ config MACH_MACKEREL
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depends on ARCH_SH7372
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select ARCH_REQUIRE_GPIOLIB
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select REGULATOR_FIXED_VOLTAGE if REGULATOR
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select SMSC_PHY if SMSC911X
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select SND_SOC_AK4642 if SND_SIMPLE_CARD
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select USE_OF
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@ -180,6 +186,7 @@ config MACH_ARMADILLO800EVA
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depends on ARCH_R8A7740
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select ARCH_REQUIRE_GPIOLIB
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select REGULATOR_FIXED_VOLTAGE if REGULATOR
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select SMSC_PHY if SH_ETH
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select SND_SOC_WM8978 if SND_SIMPLE_CARD
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select USE_OF
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@ -188,6 +195,7 @@ config MACH_ARMADILLO800EVA_REFERENCE
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depends on ARCH_R8A7740
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select ARCH_REQUIRE_GPIOLIB
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select REGULATOR_FIXED_VOLTAGE if REGULATOR
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select SMSC_PHY if SH_ETH
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select SND_SOC_WM8978 if SND_SIMPLE_CARD
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select USE_OF
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---help---
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@ -201,11 +209,11 @@ config MACH_BOCKW
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bool "BOCK-W platform"
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depends on ARCH_R8A7778
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select ARCH_REQUIRE_GPIOLIB
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select RENESAS_INTC_IRQPIN
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select REGULATOR_FIXED_VOLTAGE if REGULATOR
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select USE_OF
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select RENESAS_INTC_IRQPIN
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select SND_SOC_AK4554 if SND_SIMPLE_CARD
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select SND_SOC_AK4642 if SND_SIMPLE_CARD
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select USE_OF
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config MACH_BOCKW_REFERENCE
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bool "BOCK-W - Reference Device Tree Implementation"
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@ -242,6 +250,7 @@ config MACH_MARZEN
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depends on ARCH_R8A7779
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select ARCH_REQUIRE_GPIOLIB
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select REGULATOR_FIXED_VOLTAGE if REGULATOR
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select SMSC_PHY if SMSC911X
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select USE_OF
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config MACH_MARZEN_REFERENCE
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@ -249,6 +258,7 @@ config MACH_MARZEN_REFERENCE
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depends on ARCH_R8A7779
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select ARCH_REQUIRE_GPIOLIB
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select REGULATOR_FIXED_VOLTAGE if REGULATOR
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select SMSC_PHY if SMSC911X
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select USE_OF
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---help---
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Use reference implementation of Marzen board support
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@ -261,6 +271,7 @@ config MACH_LAGER
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bool "Lager board"
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depends on ARCH_R8A7790
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select USE_OF
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select MICREL_PHY if SH_ETH
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config MACH_KOELSCH
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bool "Koelsch board"
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@ -168,6 +168,8 @@ static struct renesas_usbhs_platform_info usbhs_info __initdata = {
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},
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.driver_param = {
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.buswait_bwait = 4,
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.d0_tx_id = HPBDMA_SLAVE_USBFUNC_TX,
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.d1_rx_id = HPBDMA_SLAVE_USBFUNC_RX,
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},
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};
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@ -332,16 +334,24 @@ static struct rsnd_ssi_platform_info rsnd_ssi[] = {
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RSND_SSI_UNUSED, /* SSI 0 */
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RSND_SSI_UNUSED, /* SSI 1 */
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RSND_SSI_UNUSED, /* SSI 2 */
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RSND_SSI_SET(1, 0, gic_iid(0x85), RSND_SSI_PLAY),
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RSND_SSI_SET(2, 0, gic_iid(0x85), RSND_SSI_CLK_PIN_SHARE),
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RSND_SSI_SET(0, 0, gic_iid(0x86), RSND_SSI_PLAY),
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RSND_SSI_SET(0, 0, gic_iid(0x86), 0),
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RSND_SSI_SET(3, 0, gic_iid(0x86), RSND_SSI_PLAY),
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RSND_SSI_SET(4, 0, gic_iid(0x86), RSND_SSI_CLK_PIN_SHARE),
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RSND_SSI_SET(1, HPBDMA_SLAVE_HPBIF3_TX, gic_iid(0x85), RSND_SSI_PLAY),
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RSND_SSI_SET(2, HPBDMA_SLAVE_HPBIF4_RX, gic_iid(0x85), RSND_SSI_CLK_PIN_SHARE),
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RSND_SSI_SET(0, HPBDMA_SLAVE_HPBIF5_TX, gic_iid(0x86), RSND_SSI_PLAY),
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RSND_SSI_SET(0, HPBDMA_SLAVE_HPBIF6_RX, gic_iid(0x86), 0),
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RSND_SSI_SET(3, HPBDMA_SLAVE_HPBIF7_TX, gic_iid(0x86), RSND_SSI_PLAY),
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RSND_SSI_SET(4, HPBDMA_SLAVE_HPBIF8_RX, gic_iid(0x86), RSND_SSI_CLK_PIN_SHARE),
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};
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static struct rsnd_scu_platform_info rsnd_scu[9] = {
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/* no member at this point */
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{ .flags = 0, }, /* SRU 0 */
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{ .flags = 0, }, /* SRU 1 */
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{ .flags = 0, }, /* SRU 2 */
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{ .flags = RSND_SCU_USE_HPBIF, },
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{ .flags = RSND_SCU_USE_HPBIF, },
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{ .flags = RSND_SCU_USE_HPBIF, },
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{ .flags = RSND_SCU_USE_HPBIF, },
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{ .flags = RSND_SCU_USE_HPBIF, },
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{ .flags = RSND_SCU_USE_HPBIF, },
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};
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enum {
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@ -45,14 +45,14 @@ static void __init koelsch_add_standard_devices(void)
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for (i = 0; i < ARRAY_SIZE(scif_names); ++i) {
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clk = clk_get(NULL, scif_names[i]);
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if (clk) {
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if (!IS_ERR(clk)) {
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clk_register_clkdev(clk, NULL, "sh-sci.%u", i);
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clk_put(clk);
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}
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}
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clk = clk_get(NULL, "cmt0");
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if (clk) {
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if (!IS_ERR(clk)) {
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clk_register_clkdev(clk, NULL, "sh_cmt.0");
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clk_put(clk);
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}
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@ -148,6 +148,21 @@ static const struct gpio_keys_platform_data koelsch_keys_pdata __initconst = {
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.nbuttons = ARRAY_SIZE(gpio_buttons),
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};
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/* SATA0 */
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static const struct resource sata0_resources[] __initconst = {
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DEFINE_RES_MEM(0xee300000, 0x2000),
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DEFINE_RES_IRQ(gic_spi(105)),
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};
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static const struct platform_device_info sata0_info __initconst = {
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.parent = &platform_bus,
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.name = "sata-r8a7791",
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.id = 0,
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.res = sata0_resources,
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.num_res = ARRAY_SIZE(sata0_resources),
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.dma_mask = DMA_BIT_MASK(32),
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};
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static const struct pinctrl_map koelsch_pinctrl_map[] = {
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/* DU */
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PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7791", "pfc-r8a7791",
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@ -192,6 +207,8 @@ static void __init koelsch_add_standard_devices(void)
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sizeof(koelsch_keys_pdata));
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koelsch_add_du_device();
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platform_device_register_full(&sata0_info);
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}
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/*
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@ -20,15 +20,14 @@
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#include <linux/init.h>
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#include <linux/of_platform.h>
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#include <linux/clk-provider.h>
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#include <mach/emev2.h>
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#include <mach/common.h>
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#include <asm/mach/arch.h>
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static void __init kzm9d_add_standard_devices(void)
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{
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if (!IS_ENABLED(CONFIG_COMMON_CLK))
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emev2_clock_init();
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of_clk_init(NULL);
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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}
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@ -44,14 +44,14 @@ static void __init lager_add_standard_devices(void)
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for (i = 0; i < ARRAY_SIZE(scif_names); ++i) {
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clk = clk_get(NULL, scif_names[i]);
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if (clk) {
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if (!IS_ERR(clk)) {
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clk_register_clkdev(clk, NULL, "sh-sci.%u", i);
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clk_put(clk);
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}
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}
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clk = clk_get(NULL, "cmt0");
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if (clk) {
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if (!IS_ERR(clk)) {
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clk_register_clkdev(clk, NULL, "sh_cmt.0");
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clk_put(clk);
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}
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@ -27,8 +27,10 @@
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#include <linux/mmc/host.h>
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#include <linux/mmc/sh_mmcif.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/platform_data/camera-rcar.h>
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#include <linux/platform_data/gpio-rcar.h>
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#include <linux/platform_data/rcar-du.h>
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#include <linux/platform_data/usb-rcar-gen2-phy.h>
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#include <linux/platform_device.h>
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#include <linux/phy.h>
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#include <linux/regulator/driver.h>
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@ -36,9 +38,12 @@
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#include <linux/regulator/gpio-regulator.h>
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#include <linux/regulator/machine.h>
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#include <linux/sh_eth.h>
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#include <linux/usb/phy.h>
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#include <linux/usb/renesas_usbhs.h>
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#include <mach/common.h>
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#include <mach/irqs.h>
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#include <mach/r8a7790.h>
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#include <media/soc_camera.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <linux/mtd/partitions.h>
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@ -263,7 +268,7 @@ static struct mtd_partition spi_flash_part[] = {
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},
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};
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static struct flash_platform_data spi_flash_data = {
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static const struct flash_platform_data spi_flash_data = {
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.name = "m25p80",
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.parts = spi_flash_part,
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.nr_parts = ARRAY_SIZE(spi_flash_part),
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@ -291,6 +296,198 @@ static const struct resource qspi_resources[] __initconst = {
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DEFINE_RES_IRQ(gic_spi(184)),
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};
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/* VIN */
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static const struct resource vin_resources[] __initconst = {
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/* VIN0 */
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DEFINE_RES_MEM(0xe6ef0000, 0x1000),
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DEFINE_RES_IRQ(gic_spi(188)),
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/* VIN1 */
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DEFINE_RES_MEM(0xe6ef1000, 0x1000),
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DEFINE_RES_IRQ(gic_spi(189)),
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};
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static void __init lager_add_vin_device(unsigned idx,
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struct rcar_vin_platform_data *pdata)
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{
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struct platform_device_info vin_info = {
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.parent = &platform_bus,
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.name = "r8a7790-vin",
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.id = idx,
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.res = &vin_resources[idx * 2],
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.num_res = 2,
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.dma_mask = DMA_BIT_MASK(32),
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.data = pdata,
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.size_data = sizeof(*pdata),
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};
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BUG_ON(idx > 1);
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platform_device_register_full(&vin_info);
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}
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#define LAGER_CAMERA(idx, name, addr, pdata, flag) \
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static struct i2c_board_info i2c_cam##idx##_device = { \
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I2C_BOARD_INFO(name, addr), \
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}; \
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\
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static struct rcar_vin_platform_data vin##idx##_pdata = { \
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.flags = flag, \
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}; \
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\
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static struct soc_camera_link cam##idx##_link = { \
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.bus_id = idx, \
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.board_info = &i2c_cam##idx##_device, \
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.i2c_adapter_id = 2, \
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.module_name = name, \
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.priv = pdata, \
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}
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/* Camera 0 is not currently supported due to adv7612 support missing */
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LAGER_CAMERA(1, "adv7180", 0x20, NULL, RCAR_VIN_BT656);
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static void __init lager_add_camera1_device(void)
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{
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platform_device_register_data(&platform_bus, "soc-camera-pdrv", 1,
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&cam1_link, sizeof(cam1_link));
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lager_add_vin_device(1, &vin1_pdata);
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}
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/* SATA1 */
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static const struct resource sata1_resources[] __initconst = {
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DEFINE_RES_MEM(0xee500000, 0x2000),
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DEFINE_RES_IRQ(gic_spi(106)),
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};
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static const struct platform_device_info sata1_info __initconst = {
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.parent = &platform_bus,
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.name = "sata-r8a7790",
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.id = 1,
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.res = sata1_resources,
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.num_res = ARRAY_SIZE(sata1_resources),
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.dma_mask = DMA_BIT_MASK(32),
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};
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/* USBHS */
|
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static const struct resource usbhs_resources[] __initconst = {
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DEFINE_RES_MEM(0xe6590000, 0x100),
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||||
DEFINE_RES_IRQ(gic_spi(107)),
|
||||
};
|
||||
|
||||
struct usbhs_private {
|
||||
struct renesas_usbhs_platform_info info;
|
||||
struct usb_phy *phy;
|
||||
};
|
||||
|
||||
#define usbhs_get_priv(pdev) \
|
||||
container_of(renesas_usbhs_get_info(pdev), struct usbhs_private, info)
|
||||
|
||||
static int usbhs_power_ctrl(struct platform_device *pdev,
|
||||
void __iomem *base, int enable)
|
||||
{
|
||||
struct usbhs_private *priv = usbhs_get_priv(pdev);
|
||||
|
||||
if (!priv->phy)
|
||||
return -ENODEV;
|
||||
|
||||
if (enable) {
|
||||
int retval = usb_phy_init(priv->phy);
|
||||
|
||||
if (!retval)
|
||||
retval = usb_phy_set_suspend(priv->phy, 0);
|
||||
return retval;
|
||||
}
|
||||
|
||||
usb_phy_set_suspend(priv->phy, 1);
|
||||
usb_phy_shutdown(priv->phy);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int usbhs_hardware_init(struct platform_device *pdev)
|
||||
{
|
||||
struct usbhs_private *priv = usbhs_get_priv(pdev);
|
||||
struct usb_phy *phy;
|
||||
|
||||
phy = usb_get_phy_dev(&pdev->dev, 0);
|
||||
if (IS_ERR(phy))
|
||||
return PTR_ERR(phy);
|
||||
|
||||
priv->phy = phy;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int usbhs_hardware_exit(struct platform_device *pdev)
|
||||
{
|
||||
struct usbhs_private *priv = usbhs_get_priv(pdev);
|
||||
|
||||
if (!priv->phy)
|
||||
return 0;
|
||||
|
||||
usb_put_phy(priv->phy);
|
||||
priv->phy = NULL;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int usbhs_get_id(struct platform_device *pdev)
|
||||
{
|
||||
return USBHS_GADGET;
|
||||
}
|
||||
|
||||
static u32 lager_usbhs_pipe_type[] = {
|
||||
USB_ENDPOINT_XFER_CONTROL,
|
||||
USB_ENDPOINT_XFER_ISOC,
|
||||
USB_ENDPOINT_XFER_ISOC,
|
||||
USB_ENDPOINT_XFER_BULK,
|
||||
USB_ENDPOINT_XFER_BULK,
|
||||
USB_ENDPOINT_XFER_BULK,
|
||||
USB_ENDPOINT_XFER_INT,
|
||||
USB_ENDPOINT_XFER_INT,
|
||||
USB_ENDPOINT_XFER_INT,
|
||||
USB_ENDPOINT_XFER_BULK,
|
||||
USB_ENDPOINT_XFER_BULK,
|
||||
USB_ENDPOINT_XFER_BULK,
|
||||
USB_ENDPOINT_XFER_BULK,
|
||||
USB_ENDPOINT_XFER_BULK,
|
||||
USB_ENDPOINT_XFER_BULK,
|
||||
USB_ENDPOINT_XFER_BULK,
|
||||
};
|
||||
|
||||
static struct usbhs_private usbhs_priv __initdata = {
|
||||
.info = {
|
||||
.platform_callback = {
|
||||
.power_ctrl = usbhs_power_ctrl,
|
||||
.hardware_init = usbhs_hardware_init,
|
||||
.hardware_exit = usbhs_hardware_exit,
|
||||
.get_id = usbhs_get_id,
|
||||
},
|
||||
.driver_param = {
|
||||
.buswait_bwait = 4,
|
||||
.pipe_type = lager_usbhs_pipe_type,
|
||||
.pipe_size = ARRAY_SIZE(lager_usbhs_pipe_type),
|
||||
},
|
||||
}
|
||||
};
|
||||
|
||||
static void __init lager_register_usbhs(void)
|
||||
{
|
||||
usb_bind_phy("renesas_usbhs", 0, "usb_phy_rcar_gen2");
|
||||
platform_device_register_resndata(&platform_bus,
|
||||
"renesas_usbhs", -1,
|
||||
usbhs_resources,
|
||||
ARRAY_SIZE(usbhs_resources),
|
||||
&usbhs_priv.info,
|
||||
sizeof(usbhs_priv.info));
|
||||
}
|
||||
|
||||
/* USBHS PHY */
|
||||
static const struct rcar_gen2_phy_platform_data usbhs_phy_pdata __initconst = {
|
||||
.chan0_pci = 0, /* Channel 0 is USBHS */
|
||||
.chan2_pci = 1, /* Channel 2 is PCI USB */
|
||||
};
|
||||
|
||||
static const struct resource usbhs_phy_resources[] __initconst = {
|
||||
DEFINE_RES_MEM(0xe6590100, 0x100),
|
||||
};
|
||||
|
||||
static const struct pinctrl_map lager_pinctrl_map[] = {
|
||||
/* DU (CN10: ARGB0, CN13: LVDS) */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7790", "pfc-r8a7790",
|
||||
|
|
@ -319,6 +516,25 @@ static const struct pinctrl_map lager_pinctrl_map[] = {
|
|||
"eth_rmii", "eth"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
|
||||
"intc_irq0", "intc"),
|
||||
/* VIN0 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
|
||||
"vin0_data24", "vin0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
|
||||
"vin0_sync", "vin0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
|
||||
"vin0_field", "vin0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
|
||||
"vin0_clkenb", "vin0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.0", "pfc-r8a7790",
|
||||
"vin0_clk", "vin0"),
|
||||
/* VIN1 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.1", "pfc-r8a7790",
|
||||
"vin1_data8", "vin1"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-vin.1", "pfc-r8a7790",
|
||||
"vin1_clk", "vin1"),
|
||||
/* USB0 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7790",
|
||||
"usb0", "usb0"),
|
||||
};
|
||||
|
||||
static void __init lager_add_standard_devices(void)
|
||||
|
|
@ -368,6 +584,17 @@ static void __init lager_add_standard_devices(void)
|
|||
&vccq_sdhi0_info, sizeof(struct gpio_regulator_config));
|
||||
platform_device_register_data(&platform_bus, "gpio-regulator", gpio_regulator_idx++,
|
||||
&vccq_sdhi2_info, sizeof(struct gpio_regulator_config));
|
||||
|
||||
lager_add_camera1_device();
|
||||
|
||||
platform_device_register_full(&sata1_info);
|
||||
|
||||
platform_device_register_resndata(&platform_bus, "usb_phy_rcar_gen2",
|
||||
-1, usbhs_phy_resources,
|
||||
ARRAY_SIZE(usbhs_phy_resources),
|
||||
&usbhs_phy_pdata,
|
||||
sizeof(usbhs_phy_pdata));
|
||||
lager_register_usbhs();
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -0,0 +1,410 @@
|
|||
LIST "KZM9G low-level initialization routine."
|
||||
LIST "Adapted from u-boot KZM9G support code."
|
||||
|
||||
LIST "Copyright (C) 2013 Ulrich Hecht"
|
||||
|
||||
LIST "This program is free software; you can redistribute it and/or modify"
|
||||
LIST "it under the terms of the GNU General Public License version 2 as"
|
||||
LIST "published by the Free Software Foundation."
|
||||
|
||||
LIST "This program is distributed in the hope that it will be useful,"
|
||||
LIST "but WITHOUT ANY WARRANTY; without even the implied warranty of"
|
||||
LIST "MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the"
|
||||
LIST "GNU General Public License for more details."
|
||||
|
||||
|
||||
LIST "Register definitions:"
|
||||
|
||||
LIST "Secure control register"
|
||||
#define LIFEC_SEC_SRC (0xE6110008)
|
||||
|
||||
LIST "RWDT"
|
||||
#define RWDT_BASE (0xE6020000)
|
||||
#define RWTCSRA0 (RWDT_BASE + 0x04)
|
||||
|
||||
LIST "HPB Semaphore Control Registers"
|
||||
#define HPBSCR_BASE (0xE6000000)
|
||||
#define HPBCTRL6 (HPBSCR_BASE + 0x1030)
|
||||
|
||||
#define SBSC1_BASE (0xFE400000)
|
||||
#define SDCR0A (SBSC1_BASE + 0x0008)
|
||||
#define SDCR1A (SBSC1_BASE + 0x000C)
|
||||
#define SDPCRA (SBSC1_BASE + 0x0010)
|
||||
#define SDCR0SA (SBSC1_BASE + 0x0018)
|
||||
#define SDCR1SA (SBSC1_BASE + 0x001C)
|
||||
#define RTCSRA (SBSC1_BASE + 0x0020)
|
||||
#define RTCORA (SBSC1_BASE + 0x0028)
|
||||
#define RTCORHA (SBSC1_BASE + 0x002C)
|
||||
#define SDWCRC0A (SBSC1_BASE + 0x0040)
|
||||
#define SDWCRC1A (SBSC1_BASE + 0x0044)
|
||||
#define SDWCR00A (SBSC1_BASE + 0x0048)
|
||||
#define SDWCR01A (SBSC1_BASE + 0x004C)
|
||||
#define SDWCR10A (SBSC1_BASE + 0x0050)
|
||||
#define SDWCR11A (SBSC1_BASE + 0x0054)
|
||||
#define SDWCR2A (SBSC1_BASE + 0x0060)
|
||||
#define SDWCRC2A (SBSC1_BASE + 0x0064)
|
||||
#define ZQCCRA (SBSC1_BASE + 0x0068)
|
||||
#define SDMRACR0A (SBSC1_BASE + 0x0084)
|
||||
#define SDMRTMPCRA (SBSC1_BASE + 0x008C)
|
||||
#define SDMRTMPMSKA (SBSC1_BASE + 0x0094)
|
||||
#define SDGENCNTA (SBSC1_BASE + 0x009C)
|
||||
#define SDDRVCR0A (SBSC1_BASE + 0x00B4)
|
||||
#define DLLCNT0A (SBSC1_BASE + 0x0354)
|
||||
|
||||
#define SDMRA1 (0xFE500000)
|
||||
#define SDMRA2 (0xFE5C0000)
|
||||
#define SDMRA3 (0xFE504000)
|
||||
|
||||
#define SBSC2_BASE (0xFB400000)
|
||||
#define SDCR0B (SBSC2_BASE + 0x0008)
|
||||
#define SDCR1B (SBSC2_BASE + 0x000C)
|
||||
#define SDPCRB (SBSC2_BASE + 0x0010)
|
||||
#define SDCR0SB (SBSC2_BASE + 0x0018)
|
||||
#define SDCR1SB (SBSC2_BASE + 0x001C)
|
||||
#define RTCSRB (SBSC2_BASE + 0x0020)
|
||||
#define RTCORB (SBSC2_BASE + 0x0028)
|
||||
#define RTCORHB (SBSC2_BASE + 0x002C)
|
||||
#define SDWCRC0B (SBSC2_BASE + 0x0040)
|
||||
#define SDWCRC1B (SBSC2_BASE + 0x0044)
|
||||
#define SDWCR00B (SBSC2_BASE + 0x0048)
|
||||
#define SDWCR01B (SBSC2_BASE + 0x004C)
|
||||
#define SDWCR10B (SBSC2_BASE + 0x0050)
|
||||
#define SDWCR11B (SBSC2_BASE + 0x0054)
|
||||
#define SDPDCR0B (SBSC2_BASE + 0x0058)
|
||||
#define SDWCR2B (SBSC2_BASE + 0x0060)
|
||||
#define SDWCRC2B (SBSC2_BASE + 0x0064)
|
||||
#define ZQCCRB (SBSC2_BASE + 0x0068)
|
||||
#define SDMRACR0B (SBSC2_BASE + 0x0084)
|
||||
#define SDMRTMPCRB (SBSC2_BASE + 0x008C)
|
||||
#define SDMRTMPMSKB (SBSC2_BASE + 0x0094)
|
||||
#define SDGENCNTB (SBSC2_BASE + 0x009C)
|
||||
#define DPHYCNT0B (SBSC2_BASE + 0x00A0)
|
||||
#define DPHYCNT1B (SBSC2_BASE + 0x00A4)
|
||||
#define DPHYCNT2B (SBSC2_BASE + 0x00A8)
|
||||
#define SDDRVCR0B (SBSC2_BASE + 0x00B4)
|
||||
#define DLLCNT0B (SBSC2_BASE + 0x0354)
|
||||
|
||||
#define SDMRB1 (0xFB500000)
|
||||
#define SDMRB2 (0xFB5C0000)
|
||||
#define SDMRB3 (0xFB504000)
|
||||
|
||||
#define CPG_BASE (0xE6150000)
|
||||
#define FRQCRA (CPG_BASE + 0x0000)
|
||||
#define FRQCRB (CPG_BASE + 0x0004)
|
||||
#define FRQCRD (CPG_BASE + 0x00E4)
|
||||
#define VCLKCR1 (CPG_BASE + 0x0008)
|
||||
#define VCLKCR2 (CPG_BASE + 0x000C)
|
||||
#define VCLKCR3 (CPG_BASE + 0x001C)
|
||||
#define ZBCKCR (CPG_BASE + 0x0010)
|
||||
#define FLCKCR (CPG_BASE + 0x0014)
|
||||
#define SD0CKCR (CPG_BASE + 0x0074)
|
||||
#define SD1CKCR (CPG_BASE + 0x0078)
|
||||
#define SD2CKCR (CPG_BASE + 0x007C)
|
||||
#define FSIACKCR (CPG_BASE + 0x0018)
|
||||
#define SUBCKCR (CPG_BASE + 0x0080)
|
||||
#define SPUACKCR (CPG_BASE + 0x0084)
|
||||
#define SPUVCKCR (CPG_BASE + 0x0094)
|
||||
#define MSUCKCR (CPG_BASE + 0x0088)
|
||||
#define HSICKCR (CPG_BASE + 0x008C)
|
||||
#define FSIBCKCR (CPG_BASE + 0x0090)
|
||||
#define MFCK1CR (CPG_BASE + 0x0098)
|
||||
#define MFCK2CR (CPG_BASE + 0x009C)
|
||||
#define DSITCKCR (CPG_BASE + 0x0060)
|
||||
#define DSI0PCKCR (CPG_BASE + 0x0064)
|
||||
#define DSI1PCKCR (CPG_BASE + 0x0068)
|
||||
#define DSI0PHYCR (CPG_BASE + 0x006C)
|
||||
#define DVFSCR3 (CPG_BASE + 0x0174)
|
||||
#define DVFSCR4 (CPG_BASE + 0x0178)
|
||||
#define DVFSCR5 (CPG_BASE + 0x017C)
|
||||
#define MPMODE (CPG_BASE + 0x00CC)
|
||||
|
||||
#define PLLECR (CPG_BASE + 0x00D0)
|
||||
#define PLL0CR (CPG_BASE + 0x00D8)
|
||||
#define PLL1CR (CPG_BASE + 0x0028)
|
||||
#define PLL2CR (CPG_BASE + 0x002C)
|
||||
#define PLL3CR (CPG_BASE + 0x00DC)
|
||||
#define PLL0STPCR (CPG_BASE + 0x00F0)
|
||||
#define PLL1STPCR (CPG_BASE + 0x00C8)
|
||||
#define PLL2STPCR (CPG_BASE + 0x00F8)
|
||||
#define PLL3STPCR (CPG_BASE + 0x00FC)
|
||||
#define RMSTPCR0 (CPG_BASE + 0x0110)
|
||||
#define RMSTPCR1 (CPG_BASE + 0x0114)
|
||||
#define RMSTPCR2 (CPG_BASE + 0x0118)
|
||||
#define RMSTPCR3 (CPG_BASE + 0x011C)
|
||||
#define RMSTPCR4 (CPG_BASE + 0x0120)
|
||||
#define RMSTPCR5 (CPG_BASE + 0x0124)
|
||||
#define SMSTPCR0 (CPG_BASE + 0x0130)
|
||||
#define SMSTPCR2 (CPG_BASE + 0x0138)
|
||||
#define SMSTPCR3 (CPG_BASE + 0x013C)
|
||||
#define CPGXXCR4 (CPG_BASE + 0x0150)
|
||||
#define SRCR0 (CPG_BASE + 0x80A0)
|
||||
#define SRCR2 (CPG_BASE + 0x80B0)
|
||||
#define SRCR3 (CPG_BASE + 0x80A8)
|
||||
#define VREFCR (CPG_BASE + 0x00EC)
|
||||
#define PCLKCR (CPG_BASE + 0x1020)
|
||||
|
||||
#define PORT32CR (0xE6051020)
|
||||
#define PORT33CR (0xE6051021)
|
||||
#define PORT34CR (0xE6051022)
|
||||
#define PORT35CR (0xE6051023)
|
||||
|
||||
LIST "DRAM initialization code:"
|
||||
|
||||
EW RWTCSRA0, 0xA507
|
||||
|
||||
ED_AND LIFEC_SEC_SRC, 0xFFFF7FFF
|
||||
|
||||
ED_AND SMSTPCR3,0xFFFF7FFF
|
||||
ED_AND SRCR3, 0xFFFF7FFF
|
||||
ED_AND SMSTPCR2,0xFFFBFFFF
|
||||
ED_AND SRCR2, 0xFFFBFFFF
|
||||
ED PLLECR, 0x00000000
|
||||
|
||||
WAIT_MASK PLLECR, 0x00000F00, 0x00000000
|
||||
WAIT_MASK FRQCRB, 0x80000000, 0x00000000
|
||||
|
||||
ED PLL0CR, 0x2D000000
|
||||
ED PLL1CR, 0x17100000
|
||||
ED FRQCRB, 0x96235880
|
||||
WAIT_MASK FRQCRB, 0x80000000, 0x00000000
|
||||
|
||||
ED FLCKCR, 0x0000000B
|
||||
ED_AND SMSTPCR0, 0xFFFFFFFD
|
||||
|
||||
ED_AND SRCR0, 0xFFFFFFFD
|
||||
ED 0xE6001628, 0x514
|
||||
ED 0xE6001648, 0x514
|
||||
ED 0xE6001658, 0x514
|
||||
ED 0xE6001678, 0x514
|
||||
|
||||
ED DVFSCR4, 0x00092000
|
||||
ED DVFSCR5, 0x000000DC
|
||||
ED PLLECR, 0x00000000
|
||||
WAIT_MASK PLLECR, 0x00000F00, 0x00000000
|
||||
|
||||
ED FRQCRA, 0x0012453C
|
||||
ED FRQCRB, 0x80431350
|
||||
WAIT_MASK FRQCRB, 0x80000000, 0x00000000
|
||||
ED FRQCRD, 0x00000B0B
|
||||
WAIT_MASK FRQCRD, 0x80000000, 0x00000000
|
||||
|
||||
ED PCLKCR, 0x00000003
|
||||
ED VCLKCR1, 0x0000012F
|
||||
ED VCLKCR2, 0x00000119
|
||||
ED VCLKCR3, 0x00000119
|
||||
ED ZBCKCR, 0x00000002
|
||||
ED FLCKCR, 0x00000005
|
||||
ED SD0CKCR, 0x00000080
|
||||
ED SD1CKCR, 0x00000080
|
||||
ED SD2CKCR, 0x00000080
|
||||
ED FSIACKCR, 0x0000003F
|
||||
ED FSIBCKCR, 0x0000003F
|
||||
ED SUBCKCR, 0x00000080
|
||||
ED SPUACKCR, 0x0000000B
|
||||
ED SPUVCKCR, 0x0000000B
|
||||
ED MSUCKCR, 0x0000013F
|
||||
ED HSICKCR, 0x00000080
|
||||
ED MFCK1CR, 0x0000003F
|
||||
ED MFCK2CR, 0x0000003F
|
||||
ED DSITCKCR, 0x00000107
|
||||
ED DSI0PCKCR, 0x00000313
|
||||
ED DSI1PCKCR, 0x0000130D
|
||||
ED DSI0PHYCR, 0x2A800E0E
|
||||
ED PLL0CR, 0x1E000000
|
||||
ED PLL0CR, 0x2D000000
|
||||
ED PLL1CR, 0x17100000
|
||||
ED PLL2CR, 0x27000080
|
||||
ED PLL3CR, 0x1D000000
|
||||
ED PLL0STPCR, 0x00080000
|
||||
ED PLL1STPCR, 0x000120C0
|
||||
ED PLL2STPCR, 0x00012000
|
||||
ED PLL3STPCR, 0x00000030
|
||||
ED PLLECR, 0x0000000B
|
||||
WAIT_MASK PLLECR, 0x00000B00, 0x00000B00
|
||||
|
||||
ED DVFSCR3, 0x000120F0
|
||||
ED MPMODE, 0x00000020
|
||||
ED VREFCR, 0x0000028A
|
||||
ED RMSTPCR0, 0xE4628087
|
||||
ED RMSTPCR1, 0xFFFFFFFF
|
||||
ED RMSTPCR2, 0x53FFFFFF
|
||||
ED RMSTPCR3, 0xFFFFFFFF
|
||||
ED RMSTPCR4, 0x00800D3D
|
||||
ED RMSTPCR5, 0xFFFFF3FF
|
||||
ED SMSTPCR2, 0x00000000
|
||||
ED SRCR2, 0x00040000
|
||||
ED_AND PLLECR, 0xFFFFFFF7
|
||||
WAIT_MASK PLLECR, 0x00000800, 0x00000000
|
||||
|
||||
LIST "set SBSC operational"
|
||||
ED HPBCTRL6, 0x00000001
|
||||
WAIT_MASK HPBCTRL6, 0x00000001, 0x00000001
|
||||
|
||||
LIST "set SBSC operating frequency"
|
||||
ED FRQCRD, 0x00001414
|
||||
WAIT_MASK FRQCRD, 0x80000000, 0x00000000
|
||||
ED PLL3CR, 0x1D000000
|
||||
ED_OR PLLECR, 0x00000008
|
||||
WAIT_MASK PLLECR, 0x00000800, 0x00000800
|
||||
|
||||
LIST "enable DLL oscillation in DDRPHY"
|
||||
ED_OR DLLCNT0A, 0x00000002
|
||||
|
||||
LIST "wait >= 100 ns"
|
||||
ED SDGENCNTA, 0x00000005
|
||||
WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000
|
||||
|
||||
LIST "target LPDDR2 device settings"
|
||||
ED SDCR0A, 0xACC90159
|
||||
ED SDCR1A, 0x00010059
|
||||
ED SDWCRC0A, 0x50874114
|
||||
ED SDWCRC1A, 0x33199B37
|
||||
ED SDWCRC2A, 0x008F2313
|
||||
ED SDWCR00A, 0x31020707
|
||||
ED SDWCR01A, 0x0017040A
|
||||
ED SDWCR10A, 0x31020707
|
||||
ED SDWCR11A, 0x0017040A
|
||||
|
||||
ED SDDRVCR0A, 0x055557ff
|
||||
|
||||
ED SDWCR2A, 0x30000000
|
||||
|
||||
LIST "drive CKE high"
|
||||
ED_OR SDPCRA, 0x00000080
|
||||
WAIT_MASK SDPCRA, 0x00000080, 0x00000080
|
||||
|
||||
LIST "wait >= 200 us"
|
||||
ED SDGENCNTA, 0x00002710
|
||||
WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000
|
||||
|
||||
LIST "issue reset command to LPDDR2 device"
|
||||
ED SDMRACR0A, 0x0000003F
|
||||
ED SDMRA1, 0x00000000
|
||||
|
||||
LIST "wait >= 10 (or 1) us (docs inconsistent)"
|
||||
ED SDGENCNTA, 0x000001F4
|
||||
WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000
|
||||
|
||||
LIST "MRW ZS initialization calibration command"
|
||||
ED SDMRACR0A, 0x0000FF0A
|
||||
ED SDMRA3, 0x00000000
|
||||
|
||||
LIST "wait >= 1 us"
|
||||
ED SDGENCNTA, 0x00000032
|
||||
WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000
|
||||
|
||||
LIST "specify operating mode in LPDDR2"
|
||||
ED SDMRACR0A, 0x00002201
|
||||
ED SDMRA1, 0x00000000
|
||||
ED SDMRACR0A, 0x00000402
|
||||
ED SDMRA1, 0x00000000
|
||||
ED SDMRACR0A, 0x00000203
|
||||
ED SDMRA1, 0x00000000
|
||||
|
||||
LIST "initialize DDR interface"
|
||||
ED SDMRA2, 0x00000000
|
||||
|
||||
LIST "temperature sensor control"
|
||||
ED SDMRTMPCRA, 0x88800004
|
||||
ED SDMRTMPMSKA,0x00000004
|
||||
|
||||
LIST "auto-refreshing control"
|
||||
ED RTCORA, 0xA55A0032
|
||||
ED RTCORHA, 0xA55A000C
|
||||
ED RTCSRA, 0xA55A2048
|
||||
|
||||
ED_OR SDCR0A, 0x00000800
|
||||
ED_OR SDCR1A, 0x00000400
|
||||
|
||||
LIST "auto ZQ calibration control"
|
||||
ED ZQCCRA, 0xFFF20000
|
||||
|
||||
ED_OR DLLCNT0B, 0x00000002
|
||||
ED SDGENCNTB, 0x00000005
|
||||
WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000
|
||||
|
||||
ED SDCR0B, 0xACC90159
|
||||
ED SDCR1B, 0x00010059
|
||||
ED SDWCRC0B, 0x50874114
|
||||
ED SDWCRC1B, 0x33199B37
|
||||
ED SDWCRC2B, 0x008F2313
|
||||
ED SDWCR00B, 0x31020707
|
||||
ED SDWCR01B, 0x0017040A
|
||||
ED SDWCR10B, 0x31020707
|
||||
ED SDWCR11B, 0x0017040A
|
||||
ED SDDRVCR0B, 0x055557ff
|
||||
ED SDWCR2B, 0x30000000
|
||||
ED_OR SDPCRB, 0x00000080
|
||||
WAIT_MASK SDPCRB, 0x00000080, 0x00000080
|
||||
|
||||
ED SDGENCNTB, 0x00002710
|
||||
WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000
|
||||
ED SDMRACR0B, 0x0000003F
|
||||
|
||||
LIST "upstream u-boot writes to SDMRA1A for both SBSC 1 and 2, which does"
|
||||
LIST "not seem to make a lot of sense..."
|
||||
ED SDMRB1, 0x00000000
|
||||
|
||||
ED SDGENCNTB, 0x000001F4
|
||||
WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000
|
||||
|
||||
ED SDMRACR0B, 0x0000FF0A
|
||||
ED SDMRB3, 0x00000000
|
||||
ED SDGENCNTB, 0x00000032
|
||||
WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000
|
||||
|
||||
ED SDMRACR0B, 0x00002201
|
||||
ED SDMRB1, 0x00000000
|
||||
ED SDMRACR0B, 0x00000402
|
||||
ED SDMRB1, 0x00000000
|
||||
ED SDMRACR0B, 0x00000203
|
||||
ED SDMRB1, 0x00000000
|
||||
ED SDMRB2, 0x00000000
|
||||
ED SDMRTMPCRB, 0x88800004
|
||||
ED SDMRTMPMSKB, 0x00000004
|
||||
ED RTCORB, 0xA55A0032
|
||||
ED RTCORHB, 0xA55A000C
|
||||
ED RTCSRB, 0xA55A2048
|
||||
ED_OR SDCR0B, 0x00000800
|
||||
ED_OR SDCR1B, 0x00000400
|
||||
ED ZQCCRB, 0xFFF20000
|
||||
ED_OR SDPDCR0B, 0x00030000
|
||||
ED DPHYCNT1B, 0xA5390000
|
||||
ED DPHYCNT0B, 0x00001200
|
||||
ED DPHYCNT1B, 0x07CE0000
|
||||
ED DPHYCNT0B, 0x00001247
|
||||
WAIT_MASK DPHYCNT2B, 0xFFFFFFFF, 0x07CE0000
|
||||
|
||||
ED_AND SDPDCR0B, 0xFFFCFFFF
|
||||
|
||||
ED FRQCRD, 0x00000B0B
|
||||
WAIT_MASK FRQCRD, 0x80000000, 0x00000000
|
||||
|
||||
ED CPGXXCR4, 0xfffffffc
|
||||
|
||||
LIST "Setup SCIF4 / workaround"
|
||||
EB PORT32CR, 0x12
|
||||
EB PORT33CR, 0x22
|
||||
EB PORT34CR, 0x12
|
||||
EB PORT35CR, 0x22
|
||||
|
||||
EW 0xE6C80000, 0
|
||||
EB 0xE6C80004, 0x19
|
||||
EW 0xE6C80008, 0x0030
|
||||
EW 0xE6C80018, 0
|
||||
EW 0xE6C80030, 0x0014
|
||||
|
||||
LIST "Magic to avoid hangs and corruption on DRAM writes."
|
||||
|
||||
LIST "It has been observed that the system would most often hang while"
|
||||
LIST "decompressing the kernel, and if it didn't it would always write"
|
||||
LIST "a corrupt image to DRAM."
|
||||
LIST "This problem does not occur in u-boot, and the reason is that"
|
||||
LIST "u-boot performs an additional cache invalidation after setting up"
|
||||
LIST "the DRAM controller. Such an invalidation should not be necessary at"
|
||||
LIST "this point, and attempts at removing parts of the routine to arrive"
|
||||
LIST "at the minimal snippet of code necessary to avoid the DRAM stability"
|
||||
LIST "problem yielded the following:"
|
||||
|
||||
MRC p15, 0, r0, c1, c0, 0
|
||||
MCR p15, 0, r0, c1, c0, 0
|
||||
|
|
@ -12,6 +12,9 @@
|
|||
#ifdef CONFIG_MACH_MACKEREL
|
||||
#define MEMORY_START 0x40000000
|
||||
#include "mach/head-mackerel.txt"
|
||||
#elif defined(CONFIG_MACH_KZM9G) || defined(CONFIG_MACH_KZM9G_REFERENCE)
|
||||
#define MEMORY_START 0x43000000
|
||||
#include "mach/head-kzm9g.txt"
|
||||
#else
|
||||
#error "unsupported board."
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -62,4 +62,47 @@
|
|||
2 :
|
||||
.endm
|
||||
|
||||
/* loop until a given value has been read (with mask) */
|
||||
.macro WAIT_MASK, addr, data, cmp
|
||||
LDR r0, 2f
|
||||
LDR r1, 3f
|
||||
LDR r2, 4f
|
||||
1:
|
||||
LDR r3, [r0, #0]
|
||||
AND r3, r1, r3
|
||||
CMP r2, r3
|
||||
BNE 1b
|
||||
B 5f
|
||||
2: .long \addr
|
||||
3: .long \data
|
||||
4: .long \cmp
|
||||
5:
|
||||
.endm
|
||||
|
||||
/* read 32-bit value from addr, "or" an immediate and write back */
|
||||
.macro ED_OR, addr, data
|
||||
LDR r4, 1f
|
||||
LDR r5, 2f
|
||||
LDR r6, [r4]
|
||||
ORR r5, r6, r5
|
||||
STR r5, [r4]
|
||||
B 3f
|
||||
1: .long \addr
|
||||
2: .long \data
|
||||
3:
|
||||
.endm
|
||||
|
||||
/* read 32-bit value from addr, "and" an immediate and write back */
|
||||
.macro ED_AND, addr, data
|
||||
LDR r4, 1f
|
||||
LDR r5, 2f
|
||||
LDR r6, [r4]
|
||||
AND r5, r6, r5
|
||||
STR r5, [r4]
|
||||
B 3f
|
||||
1: .long \addr
|
||||
2: .long \data
|
||||
3:
|
||||
.endm
|
||||
|
||||
#endif /* __ZBOOT_MACRO_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue