Merge series "spi: stm32: various fixes & cleanup" from Alain Volmat <alain.volmat@foss.st.com>:
This series contains fixes & cleanup mainly regarding fifo
and the way end of transfer triggered, when used with or
without DMA.
An additional patch cleans up the pm_runtime calls and another
one enables the autosuspend.
v2: - split pm_runtime fix patch into two
- correct revert commit subject line
Alain Volmat (6):
spi: stm32: fixes pm_runtime calls in probe/remove
spi: stm32: enable pm_runtime autosuspend
spi: stm32h7: fix full duplex irq handler handling
spi: stm32: Revert "properly handle 0 byte transfer"
spi: stm32h7: don't wait for EOT and flush fifo on disable
spi: stm32: finalize message either on dma callback or EOT
Amelie Delaunay (1):
spi: stm32h7: rework rx fifo read function
drivers/spi/spi-stm32.c | 146 +++++++++++++++++-----------------------
1 file changed, 61 insertions(+), 85 deletions(-)
--
2.25.1
This commit is contained in:
Mark Brown
commit
65ab894f2e
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@ -162,6 +162,8 @@
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#define SPI_3WIRE_TX 3
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#define SPI_3WIRE_RX 4
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#define STM32_SPI_AUTOSUSPEND_DELAY 1 /* 1 ms */
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/*
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* use PIO for small transfers, avoiding DMA setup/teardown overhead for drivers
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* without fifo buffers.
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@ -568,29 +570,30 @@ static void stm32f4_spi_read_rx(struct stm32_spi *spi)
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/**
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* stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
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* @spi: pointer to the spi controller data structure
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* @flush: boolean indicating that FIFO should be flushed
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*
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* Write in rx_buf depends on remaining bytes to avoid to write beyond
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* rx_buf end.
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*/
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static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
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static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi)
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{
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u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
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u32 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
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while ((spi->rx_len > 0) &&
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((sr & STM32H7_SPI_SR_RXP) ||
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(flush && ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) {
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((sr & STM32H7_SPI_SR_EOT) &&
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((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) {
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u32 offs = spi->cur_xferlen - spi->rx_len;
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if ((spi->rx_len >= sizeof(u32)) ||
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(flush && (sr & STM32H7_SPI_SR_RXWNE))) {
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(sr & STM32H7_SPI_SR_RXWNE)) {
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u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs);
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*rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR);
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spi->rx_len -= sizeof(u32);
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} else if ((spi->rx_len >= sizeof(u16)) ||
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(flush && (rxplvl >= 2 || spi->cur_bpw > 8))) {
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(!(sr & STM32H7_SPI_SR_RXWNE) &&
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(rxplvl >= 2 || spi->cur_bpw > 8))) {
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u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
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*rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR);
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@ -606,8 +609,8 @@ static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
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rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
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}
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dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
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flush ? "(flush)" : "", spi->rx_len);
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dev_dbg(spi->dev, "%s: %d bytes left (sr=%08x)\n",
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__func__, spi->rx_len, sr);
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}
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/**
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@ -674,18 +677,12 @@ static void stm32f4_spi_disable(struct stm32_spi *spi)
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* stm32h7_spi_disable - Disable SPI controller
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* @spi: pointer to the spi controller data structure
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*
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* RX-Fifo is flushed when SPI controller is disabled. To prevent any data
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* loss, use stm32h7_spi_read_rxfifo(flush) to read the remaining bytes in
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* RX-Fifo.
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* Normally, if TSIZE has been configured, we should relax the hardware at the
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* reception of the EOT interrupt. But in case of error, EOT will not be
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* raised. So the subsystem unprepare_message call allows us to properly
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* complete the transfer from an hardware point of view.
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* RX-Fifo is flushed when SPI controller is disabled.
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*/
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static void stm32h7_spi_disable(struct stm32_spi *spi)
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{
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unsigned long flags;
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u32 cr1, sr;
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u32 cr1;
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dev_dbg(spi->dev, "disable controller\n");
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@ -698,25 +695,6 @@ static void stm32h7_spi_disable(struct stm32_spi *spi)
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return;
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}
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/* Wait on EOT or suspend the flow */
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if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR,
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sr, !(sr & STM32H7_SPI_SR_EOT),
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10, 100000) < 0) {
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if (cr1 & STM32H7_SPI_CR1_CSTART) {
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writel_relaxed(cr1 | STM32H7_SPI_CR1_CSUSP,
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spi->base + STM32H7_SPI_CR1);
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if (readl_relaxed_poll_timeout_atomic(
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spi->base + STM32H7_SPI_SR,
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sr, !(sr & STM32H7_SPI_SR_SUSP),
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10, 100000) < 0)
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dev_warn(spi->dev,
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"Suspend request timeout\n");
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}
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}
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if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0))
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stm32h7_spi_read_rxfifo(spi, true);
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if (spi->cur_usedma && spi->dma_tx)
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dmaengine_terminate_all(spi->dma_tx);
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if (spi->cur_usedma && spi->dma_rx)
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@ -911,7 +889,7 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
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if (__ratelimit(&rs))
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dev_dbg_ratelimited(spi->dev, "Communication suspended\n");
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if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
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stm32h7_spi_read_rxfifo(spi, false);
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stm32h7_spi_read_rxfifo(spi);
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/*
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* If communication is suspended while using DMA, it means
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* that something went wrong, so stop the current transfer
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@ -932,8 +910,11 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
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if (sr & STM32H7_SPI_SR_EOT) {
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if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
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stm32h7_spi_read_rxfifo(spi, true);
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end = true;
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stm32h7_spi_read_rxfifo(spi);
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if (!spi->cur_usedma ||
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(spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX ||
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spi->cur_comm == SPI_3WIRE_TX)))
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end = true;
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}
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if (sr & STM32H7_SPI_SR_TXP)
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@ -942,7 +923,7 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
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if (sr & STM32H7_SPI_SR_RXP)
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if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
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stm32h7_spi_read_rxfifo(spi, false);
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stm32h7_spi_read_rxfifo(spi);
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writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR);
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@ -1041,42 +1022,17 @@ static void stm32f4_spi_dma_tx_cb(void *data)
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}
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/**
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* stm32f4_spi_dma_rx_cb - dma callback
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* stm32_spi_dma_rx_cb - dma callback
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* @data: pointer to the spi controller data structure
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*
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* DMA callback is called when the transfer is complete for DMA RX channel.
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*/
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static void stm32f4_spi_dma_rx_cb(void *data)
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static void stm32_spi_dma_rx_cb(void *data)
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{
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struct stm32_spi *spi = data;
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spi_finalize_current_transfer(spi->master);
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stm32f4_spi_disable(spi);
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}
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/**
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* stm32h7_spi_dma_cb - dma callback
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* @data: pointer to the spi controller data structure
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*
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* DMA callback is called when the transfer is complete or when an error
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* occurs. If the transfer is complete, EOT flag is raised.
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*/
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static void stm32h7_spi_dma_cb(void *data)
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{
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struct stm32_spi *spi = data;
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unsigned long flags;
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u32 sr;
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spin_lock_irqsave(&spi->lock, flags);
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sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
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spin_unlock_irqrestore(&spi->lock, flags);
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if (!(sr & STM32H7_SPI_SR_EOT))
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dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr);
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/* Now wait for EOT, or SUSP or OVR in case of error */
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spi->cfg->disable(spi);
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}
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/**
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@ -1242,11 +1198,13 @@ static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi)
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*/
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static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi)
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{
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/* Enable the interrupts relative to the end of transfer */
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stm32_spi_set_bits(spi, STM32H7_SPI_IER, STM32H7_SPI_IER_EOTIE |
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STM32H7_SPI_IER_TXTFIE |
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STM32H7_SPI_IER_OVRIE |
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STM32H7_SPI_IER_MODFIE);
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uint32_t ier = STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
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/* Enable the interrupts */
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if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX)
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ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE;
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stm32_spi_set_bits(spi, STM32H7_SPI_IER, ier);
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stm32_spi_enable(spi);
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@ -1645,10 +1603,6 @@ static int stm32_spi_transfer_one(struct spi_master *master,
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struct stm32_spi *spi = spi_master_get_devdata(master);
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int ret;
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/* Don't do anything on 0 bytes transfers */
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if (transfer->len == 0)
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return 0;
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spi->tx_buf = transfer->tx_buf;
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spi->rx_buf = transfer->rx_buf;
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spi->tx_len = spi->tx_buf ? transfer->len : 0;
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@ -1762,7 +1716,7 @@ static const struct stm32_spi_cfg stm32f4_spi_cfg = {
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.set_mode = stm32f4_spi_set_mode,
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.transfer_one_dma_start = stm32f4_spi_transfer_one_dma_start,
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.dma_tx_cb = stm32f4_spi_dma_tx_cb,
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.dma_rx_cb = stm32f4_spi_dma_rx_cb,
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.dma_rx_cb = stm32_spi_dma_rx_cb,
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.transfer_one_irq = stm32f4_spi_transfer_one_irq,
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.irq_handler_event = stm32f4_spi_irq_event,
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.irq_handler_thread = stm32f4_spi_irq_thread,
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@ -1782,8 +1736,11 @@ static const struct stm32_spi_cfg stm32h7_spi_cfg = {
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.set_data_idleness = stm32h7_spi_data_idleness,
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.set_number_of_data = stm32h7_spi_number_of_data,
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.transfer_one_dma_start = stm32h7_spi_transfer_one_dma_start,
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.dma_rx_cb = stm32h7_spi_dma_cb,
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.dma_tx_cb = stm32h7_spi_dma_cb,
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.dma_rx_cb = stm32_spi_dma_rx_cb,
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/*
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* dma_tx_cb is not necessary since in case of TX, dma is followed by
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* SPI access hence handling is performed within the SPI interrupt
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*/
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.transfer_one_irq = stm32h7_spi_transfer_one_irq,
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.irq_handler_thread = stm32h7_spi_irq_thread,
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.baud_rate_div_min = STM32H7_SPI_MBR_DIV_MIN,
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@ -1927,6 +1884,9 @@ static int stm32_spi_probe(struct platform_device *pdev)
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if (spi->dma_tx || spi->dma_rx)
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master->can_dma = stm32_spi_can_dma;
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pm_runtime_set_autosuspend_delay(&pdev->dev,
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STM32_SPI_AUTOSUSPEND_DELAY);
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pm_runtime_use_autosuspend(&pdev->dev);
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pm_runtime_set_active(&pdev->dev);
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pm_runtime_get_noresume(&pdev->dev);
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pm_runtime_enable(&pdev->dev);
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@ -1938,6 +1898,9 @@ static int stm32_spi_probe(struct platform_device *pdev)
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goto err_pm_disable;
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}
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pm_runtime_mark_last_busy(&pdev->dev);
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pm_runtime_put_autosuspend(&pdev->dev);
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dev_info(&pdev->dev, "driver initialized\n");
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return 0;
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@ -1946,6 +1909,7 @@ err_pm_disable:
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pm_runtime_disable(&pdev->dev);
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pm_runtime_put_noidle(&pdev->dev);
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pm_runtime_set_suspended(&pdev->dev);
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pm_runtime_dont_use_autosuspend(&pdev->dev);
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err_dma_release:
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if (spi->dma_tx)
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dma_release_channel(spi->dma_tx);
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@ -1970,6 +1934,8 @@ static int stm32_spi_remove(struct platform_device *pdev)
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pm_runtime_disable(&pdev->dev);
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pm_runtime_put_noidle(&pdev->dev);
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pm_runtime_set_suspended(&pdev->dev);
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pm_runtime_dont_use_autosuspend(&pdev->dev);
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if (master->dma_tx)
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dma_release_channel(master->dma_tx);
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if (master->dma_rx)
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