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drm/amd/display: Fix incorrect backlight register offset for DCN 

[Why]
Typo in backlight refactor introduced wrong register offset.

[How]
SR(BIOS_SCRATCH_2) to NBIO_SR(BIOS_SCRATCH_2).

Signed-off-by: David Galiffi <David.Galiffi@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: <stable@vger.kernel.org>
This commit is contained in:
David Galiffi 2020-09-03 19:20:36 -04:00 committed by Alex Deucher
parent d0e63b343e
commit 651111be24
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h
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@ -54,7 +54,7 @@
SR(BL_PWM_CNTL2), \
SR(BL_PWM_PERIOD_CNTL), \
SR(BL_PWM_GRP1_REG_LOCK), \
SR(BIOS_SCRATCH_2)
NBIO_SR(BIOS_SCRATCH_2)
#define DCE_PANEL_CNTL_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix