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drm/amdgpu/gfx10: add support for navy_flounder firmware 

Declare the gfx/compute firmwares.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jiansong Chen 2020-02-10 15:21:09 +08:00 committed by Alex Deucher
parent 41f446bf52
commit 6501019304
1 changed files with 10 additions and 0 deletions
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10
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
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@ -145,6 +145,13 @@ MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
static const struct soc15_reg_golden golden_settings_gc_10_1[] = static const struct soc15_reg_golden golden_settings_gc_10_1[] =
{ {
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
@ -3578,6 +3585,9 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
case CHIP_SIENNA_CICHLID: case CHIP_SIENNA_CICHLID:
chip_name = "sienna_cichlid"; chip_name = "sienna_cichlid";
break; break;
case CHIP_NAVY_FLOUNDER:
chip_name = "navy_flounder";
break;
default: default:
BUG(); BUG();
} }