UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

ARM: dts: stm32: add sdmmc2 & 3 nodes for STM32MP157 SoC 

The STM32MP157 SoC series includes 3 instances of the SDMMC peripheral.
The sdmmc2 and sdmmc3 nodes are added in STM32MP157 SoC DT file.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
This commit is contained in:
Yann Gautier 2019-11-06 11:09:36 +01:00 committed by Alexandre Torgue
parent 0a1732cf6c
commit 64e11cb783
1 changed files with 32 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
arch/arm/boot/dts/stm32mp157c.dtsi
View File

@ -1060,6 +1060,21 @@
}; };
}; };
sdmmc3: sdmmc@48004000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x10153180>;
reg = <0x48004000 0x400>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC3_K>;
clock-names = "apb_pclk";
resets = <&rcc SDMMC3_R>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <120000000>;
status = "disabled";
};
usbotg_hs: usb-otg@49000000 { usbotg_hs: usb-otg@49000000 {
compatible = "snps,dwc2"; compatible = "snps,dwc2";
reg = <0x49000000 0x10000>; reg = <0x49000000 0x10000>;
@ -1348,13 +1363,29 @@
arm,primecell-periphid = <0x10153180>; arm,primecell-periphid = <0x10153180>;
reg = <0x58005000 0x1000>; reg = <0x58005000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq"; interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC1_K>; clocks = <&rcc SDMMC1_K>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
resets = <&rcc SDMMC1_R>; resets = <&rcc SDMMC1_R>;
cap-sd-highspeed; cap-sd-highspeed;
cap-mmc-highspeed; cap-mmc-highspeed;
max-frequency = <120000000>; max-frequency = <120000000>;
status = "disabled";
};
sdmmc2: sdmmc@58007000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x10153180>;
reg = <0x58007000 0x1000>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC2_K>;
clock-names = "apb_pclk";
resets = <&rcc SDMMC2_R>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <120000000>;
status = "disabled";
}; };
crc1: crc@58009000 { crc1: crc@58009000 {