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ARM: dts: socfpga: Add Altera Arria10 L2 Cache EDAC devicetree entry 

Add the device tree entries needed to support the Altera L2
cache EDAC on the Arria10 chip.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
This commit is contained in:
Thor Thayer 2016-03-21 16:01:46 +00:00 committed by Dinh Nguyen
parent 95c16caaa8
commit 64ded09d29
1 changed files with 15 additions and 0 deletions
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15
arch/arm/boot/dts/socfpga_arria10.dtsi
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@ -603,6 +603,21 @@
reg = <0xffe00000 0x40000>;
};
eccmgr: eccmgr@ffd06000 {
compatible = "altr,socfpga-a10-ecc-manager";
altr,sysmgr-syscon = <&sysmgr>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
<0 0 IRQ_TYPE_LEVEL_HIGH>;
ranges;
l2-ecc@ffd06010 {
compatible = "altr,socfpga-a10-l2-ecc";
reg = <0xffd06010 0x4>;
};
};
rst: rstmgr@ffd05000 {
#reset-cells = <1>;
compatible = "altr,rst-mgr";