UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

drm/vc4: crtc: Add FIFO depth to vc4_crtc_data 

Not all pixelvalve FIFOs in vc5 have the same depth, so we need to add that
to our vc4_crtc_data structure to be able to compute the fill level
properly later on.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/7df3549c1bea9b0a27c784dc416bb9a831e4e18f.1599120059.git-series.maxime@cerno.tech
This commit is contained in:
Maxime Ripard 2020-09-03 10:00:47 +02:00
parent 87ebcd42fb
commit 649abf2f5d
No known key found for this signature in database
GPG Key ID: E3EF0D6F671851C5
2 changed files with 20 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
drivers/gpu/drm/vc4/vc4_crtc.c
View File

@ -206,10 +206,21 @@ void vc4_crtc_destroy(struct drm_crtc *crtc)
drm_crtc_cleanup(crtc);
}
static u32 vc4_get_fifo_full_level(u32 format)
static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
{
static const u32 fifo_len_bytes = 64;
const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
u32 fifo_len_bytes = pv_data->fifo_depth;
/*
* Pixels are pulled from the HVS if the number of bytes is
* lower than the FIFO full level.
*
* The latency of the pixel fetch mechanism is 6 pixels, so we
* need to convert those 6 pixels in bytes, depending on the
* format, and then subtract that from the length of the FIFO
* to make sure we never end up in a situation where the FIFO
* is full.
*/
switch (format) {
case PV_CONTROL_FORMAT_DSIV_16:
case PV_CONTROL_FORMAT_DSIC_16:
@ -326,7 +337,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc)
CRTC_WRITE(PV_CONTROL,
VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
VC4_SET_FIELD(vc4_get_fifo_full_level(format),
VC4_SET_FIELD(vc4_get_fifo_full_level(vc4_crtc, format),
PV_CONTROL_FIFO_LEVEL) |
VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
PV_CONTROL_CLR_AT_START |
@ -785,6 +796,7 @@ static const struct vc4_pv_data bcm2835_pv0_data = {
.hvs_output = 0,
},
.debugfs_name = "crtc0_regs",
.fifo_depth = 64,
.pixels_per_clock = 1,
.encoder_types = {
[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
@ -798,6 +810,7 @@ static const struct vc4_pv_data bcm2835_pv1_data = {
.hvs_output = 2,
},
.debugfs_name = "crtc1_regs",
.fifo_depth = 64,
.pixels_per_clock = 1,
.encoder_types = {
[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
@ -811,6 +824,7 @@ static const struct vc4_pv_data bcm2835_pv2_data = {
.hvs_output = 1,
},
.debugfs_name = "crtc2_regs",
.fifo_depth = 64,
.pixels_per_clock = 1,
.encoder_types = {
[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,

3
drivers/gpu/drm/vc4/vc4_drv.h
View File

@ -457,6 +457,9 @@ struct vc4_crtc_data {
struct vc4_pv_data {
struct vc4_crtc_data base;
/* Depth of the PixelValve FIFO in bytes */
unsigned int fifo_depth;
/* Number of pixels output per clock period */
u8 pixels_per_clock;