Merge branch 'hns-roce' into k.o/for-4.9
This commit is contained in:
commit
64278fe89b
|
@ -531,7 +531,7 @@ struct hns_roce_dev {
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struct ib_device ib_dev;
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struct platform_device *pdev;
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struct hns_roce_uar priv_uar;
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const char *irq_names;
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const char *irq_names[HNS_ROCE_MAX_IRQ_NUM];
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spinlock_t sm_lock;
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spinlock_t cq_db_lock;
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spinlock_t bt_cmd_lock;
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@ -713,7 +713,7 @@ int hns_roce_init_eq_table(struct hns_roce_dev *hr_dev)
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for (j = 0; j < eq_num; j++) {
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ret = request_irq(eq_table->eq[j].irq, hns_roce_msi_x_interrupt,
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0, hr_dev->irq_names, eq_table->eq + j);
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0, hr_dev->irq_names[j], eq_table->eq + j);
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if (ret) {
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dev_err(dev, "request irq error!\n");
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goto err_request_irq_fail;
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@ -31,6 +31,7 @@
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*/
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#include <linux/platform_device.h>
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#include <linux/acpi.h>
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#include <rdma/ib_umem.h>
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#include "hns_roce_common.h"
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#include "hns_roce_device.h"
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@ -794,29 +795,47 @@ static void hns_roce_port_enable(struct hns_roce_dev *hr_dev, int enable_flag)
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* @enable: true -- drop reset, false -- reset
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* return 0 - success , negative --fail
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*/
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int hns_roce_v1_reset(struct hns_roce_dev *hr_dev, bool enable)
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int hns_roce_v1_reset(struct hns_roce_dev *hr_dev, bool dereset)
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{
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struct device_node *dsaf_node;
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struct device *dev = &hr_dev->pdev->dev;
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struct device_node *np = dev->of_node;
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struct fwnode_handle *fwnode;
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int ret;
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dsaf_node = of_parse_phandle(np, "dsaf-handle", 0);
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if (!dsaf_node) {
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dev_err(dev, "Unable to get dsaf node by dsaf-handle!\n");
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return -EINVAL;
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/* check if this is DT/ACPI case */
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if (dev_of_node(dev)) {
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dsaf_node = of_parse_phandle(np, "dsaf-handle", 0);
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if (!dsaf_node) {
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dev_err(dev, "could not find dsaf-handle\n");
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return -EINVAL;
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}
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fwnode = &dsaf_node->fwnode;
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} else if (is_acpi_device_node(dev->fwnode)) {
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struct acpi_reference_args args;
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ret = acpi_node_get_property_reference(dev->fwnode,
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"dsaf-handle", 0, &args);
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if (ret) {
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dev_err(dev, "could not find dsaf-handle\n");
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return ret;
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}
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fwnode = acpi_fwnode_handle(args.adev);
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} else {
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dev_err(dev, "cannot read data from DT or ACPI\n");
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return -ENXIO;
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}
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ret = hns_dsaf_roce_reset(&dsaf_node->fwnode, false);
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ret = hns_dsaf_roce_reset(fwnode, false);
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if (ret)
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return ret;
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if (enable) {
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if (dereset) {
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msleep(SLEEP_TIME_INTERVAL);
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return hns_dsaf_roce_reset(&dsaf_node->fwnode, true);
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ret = hns_dsaf_roce_reset(fwnode, true);
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}
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return 0;
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return ret;
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}
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void hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
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@ -976,6 +976,6 @@ struct hns_roce_v1_priv {
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struct hns_roce_raq_table raq_table;
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};
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int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool enable);
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int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset);
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#endif
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@ -30,7 +30,7 @@
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/acpi.h>
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#include <linux/of_platform.h>
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#include <rdma/ib_addr.h>
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#include <rdma/ib_smi.h>
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@ -694,40 +694,122 @@ error_failed_setup_mtu_gids:
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return ret;
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}
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static const struct of_device_id hns_roce_of_match[] = {
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{ .compatible = "hisilicon,hns-roce-v1", .data = &hns_roce_hw_v1, },
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{},
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};
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MODULE_DEVICE_TABLE(of, hns_roce_of_match);
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static const struct acpi_device_id hns_roce_acpi_match[] = {
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{ "HISI00D1", (kernel_ulong_t)&hns_roce_hw_v1 },
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{},
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};
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MODULE_DEVICE_TABLE(acpi, hns_roce_acpi_match);
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static int hns_roce_node_match(struct device *dev, void *fwnode)
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{
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return dev->fwnode == fwnode;
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}
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static struct
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platform_device *hns_roce_find_pdev(struct fwnode_handle *fwnode)
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{
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struct device *dev;
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/* get the 'device'corresponding to matching 'fwnode' */
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dev = bus_find_device(&platform_bus_type, NULL,
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fwnode, hns_roce_node_match);
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/* get the platform device */
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return dev ? to_platform_device(dev) : NULL;
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}
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static int hns_roce_get_cfg(struct hns_roce_dev *hr_dev)
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{
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int i;
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int ret;
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u8 phy_port;
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int port_cnt = 0;
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struct device *dev = &hr_dev->pdev->dev;
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struct device_node *np = dev->of_node;
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struct device_node *net_node;
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struct net_device *netdev = NULL;
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struct platform_device *pdev = NULL;
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struct resource *res;
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if (of_device_is_compatible(np, "hisilicon,hns-roce-v1")) {
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hr_dev->hw = &hns_roce_hw_v1;
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/* check if we are compatible with the underlying SoC */
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if (dev_of_node(dev)) {
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const struct of_device_id *of_id;
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of_id = of_match_node(hns_roce_of_match, dev->of_node);
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if (!of_id) {
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dev_err(dev, "device is not compatible!\n");
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return -ENXIO;
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}
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hr_dev->hw = (struct hns_roce_hw *)of_id->data;
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if (!hr_dev->hw) {
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dev_err(dev, "couldn't get H/W specific DT data!\n");
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return -ENXIO;
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}
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} else if (is_acpi_device_node(dev->fwnode)) {
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const struct acpi_device_id *acpi_id;
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acpi_id = acpi_match_device(hns_roce_acpi_match, dev);
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if (!acpi_id) {
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dev_err(dev, "device is not compatible!\n");
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return -ENXIO;
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}
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hr_dev->hw = (struct hns_roce_hw *) acpi_id->driver_data;
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if (!hr_dev->hw) {
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dev_err(dev, "couldn't get H/W specific ACPI data!\n");
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return -ENXIO;
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}
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} else {
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dev_err(dev, "device no compatible!\n");
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return -EINVAL;
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dev_err(dev, "can't read compatibility data from DT or ACPI\n");
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return -ENXIO;
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}
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/* get the mapped register base address */
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res = platform_get_resource(hr_dev->pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(dev, "memory resource not found!\n");
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return -EINVAL;
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}
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hr_dev->reg_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(hr_dev->reg_base))
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return PTR_ERR(hr_dev->reg_base);
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/* get the RoCE associated ethernet ports or netdevices */
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for (i = 0; i < HNS_ROCE_MAX_PORTS; i++) {
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net_node = of_parse_phandle(np, "eth-handle", i);
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if (net_node) {
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if (dev_of_node(dev)) {
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net_node = of_parse_phandle(dev->of_node, "eth-handle",
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i);
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if (!net_node)
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continue;
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pdev = of_find_device_by_node(net_node);
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} else if (is_acpi_device_node(dev->fwnode)) {
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struct acpi_reference_args args;
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struct fwnode_handle *fwnode;
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ret = acpi_node_get_property_reference(dev->fwnode,
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"eth-handle",
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i, &args);
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if (ret)
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continue;
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fwnode = acpi_fwnode_handle(args.adev);
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pdev = hns_roce_find_pdev(fwnode);
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} else {
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dev_err(dev, "cannot read data from DT or ACPI\n");
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return -ENXIO;
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}
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if (pdev) {
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netdev = platform_get_drvdata(pdev);
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phy_port = (u8)i;
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if (netdev) {
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hr_dev->iboe.netdevs[port_cnt] = netdev;
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hr_dev->iboe.phy_port[port_cnt] = phy_port;
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} else {
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dev_err(dev, "no netdev found with pdev %s\n",
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pdev->name);
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return -ENODEV;
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}
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port_cnt++;
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@ -735,26 +817,32 @@ static int hns_roce_get_cfg(struct hns_roce_dev *hr_dev)
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}
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if (port_cnt == 0) {
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dev_err(dev, "Unable to get available port by eth-handle!\n");
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dev_err(dev, "unable to get eth-handle for available ports!\n");
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return -EINVAL;
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}
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hr_dev->caps.num_ports = port_cnt;
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/* Cmd issue mode: 0 is poll, 1 is event */
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/* cmd issue mode: 0 is poll, 1 is event */
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hr_dev->cmd_mod = 1;
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hr_dev->loop_idc = 0;
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/* read the interrupt names from the DT or ACPI */
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ret = device_property_read_string_array(dev, "interrupt-names",
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hr_dev->irq_names,
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HNS_ROCE_MAX_IRQ_NUM);
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if (ret < 0) {
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dev_err(dev, "couldn't get interrupt names from DT or ACPI!\n");
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return ret;
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}
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/* fetch the interrupt numbers */
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for (i = 0; i < HNS_ROCE_MAX_IRQ_NUM; i++) {
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hr_dev->irq[i] = platform_get_irq(hr_dev->pdev, i);
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if (hr_dev->irq[i] <= 0) {
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dev_err(dev, "Get No.%d irq resource failed!\n", i);
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dev_err(dev, "platform get of irq[=%d] failed!\n", i);
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return -EINVAL;
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}
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if (of_property_read_string_index(np, "interrupt-names", i,
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&hr_dev->irq_names))
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return -EINVAL;
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}
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return 0;
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@ -917,7 +1005,7 @@ static int hns_roce_probe(struct platform_device *pdev)
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if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64ULL)) &&
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dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32ULL))) {
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dev_err(dev, "No usable DMA addressing mode\n");
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dev_err(dev, "Not usable DMA addressing mode\n");
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ret = -EIO;
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goto error_failed_get_cfg;
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}
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@ -1035,18 +1123,13 @@ static int hns_roce_remove(struct platform_device *pdev)
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return 0;
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}
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static const struct of_device_id hns_roce_of_match[] = {
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{ .compatible = "hisilicon,hns-roce-v1",},
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{},
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};
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MODULE_DEVICE_TABLE(of, hns_roce_of_match);
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static struct platform_driver hns_roce_driver = {
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.probe = hns_roce_probe,
|
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.remove = hns_roce_remove,
|
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.driver = {
|
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.name = DRV_NAME,
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.of_match_table = hns_roce_of_match,
|
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.acpi_match_table = ACPI_PTR(hns_roce_acpi_match),
|
||||
},
|
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};
|
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|
||||
|
|
|
@ -644,21 +644,6 @@ hns_mac_phy_parse_addr(struct device *dev, struct fwnode_handle *fwnode)
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return addr;
|
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}
|
||||
|
||||
static int hns_mac_phydev_match(struct device *dev, void *fwnode)
|
||||
{
|
||||
return dev->fwnode == fwnode;
|
||||
}
|
||||
|
||||
static struct
|
||||
platform_device *hns_mac_find_platform_device(struct fwnode_handle *fwnode)
|
||||
{
|
||||
struct device *dev;
|
||||
|
||||
dev = bus_find_device(&platform_bus_type, NULL,
|
||||
fwnode, hns_mac_phydev_match);
|
||||
return dev ? to_platform_device(dev) : NULL;
|
||||
}
|
||||
|
||||
static int
|
||||
hns_mac_register_phydev(struct mii_bus *mdio, struct hns_mac_cb *mac_cb,
|
||||
u32 addr)
|
||||
|
@ -724,7 +709,7 @@ static void hns_mac_register_phy(struct hns_mac_cb *mac_cb)
|
|||
return;
|
||||
|
||||
/* dev address in adev */
|
||||
pdev = hns_mac_find_platform_device(acpi_fwnode_handle(args.adev));
|
||||
pdev = hns_dsaf_find_platform_device(acpi_fwnode_handle(args.adev));
|
||||
mii_bus = platform_get_drvdata(pdev);
|
||||
rc = hns_mac_register_phydev(mii_bus, mac_cb, addr);
|
||||
if (!rc)
|
||||
|
|
|
@ -2788,7 +2788,7 @@ module_platform_driver(g_dsaf_driver);
|
|||
* @enable: false - request reset , true - drop reset
|
||||
* retuen 0 - success , negative -fail
|
||||
*/
|
||||
int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool enable)
|
||||
int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset)
|
||||
{
|
||||
struct dsaf_device *dsaf_dev;
|
||||
struct platform_device *pdev;
|
||||
|
@ -2817,24 +2817,44 @@ int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool enable)
|
|||
{DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},
|
||||
};
|
||||
|
||||
if (!is_of_node(dsaf_fwnode)) {
|
||||
pr_err("hisi_dsaf: Only support DT node!\n");
|
||||
/* find the platform device corresponding to fwnode */
|
||||
if (is_of_node(dsaf_fwnode)) {
|
||||
pdev = of_find_device_by_node(to_of_node(dsaf_fwnode));
|
||||
} else if (is_acpi_device_node(dsaf_fwnode)) {
|
||||
pdev = hns_dsaf_find_platform_device(dsaf_fwnode);
|
||||
} else {
|
||||
pr_err("fwnode is neither OF or ACPI type\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
pdev = of_find_device_by_node(to_of_node(dsaf_fwnode));
|
||||
|
||||
/* check if we were a success in fetching pdev */
|
||||
if (!pdev) {
|
||||
pr_err("couldn't find platform device for node\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* retrieve the dsaf_device from the driver data */
|
||||
dsaf_dev = dev_get_drvdata(&pdev->dev);
|
||||
if (!dsaf_dev) {
|
||||
dev_err(&pdev->dev, "dsaf_dev is NULL\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* now, make sure we are running on compatible SoC */
|
||||
if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
|
||||
dev_err(dsaf_dev->dev, "%s v1 chip doesn't support RoCE!\n",
|
||||
dsaf_dev->ae_dev.name);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (!enable) {
|
||||
/* Reset rocee-channels in dsaf and rocee */
|
||||
hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK, false);
|
||||
hns_dsaf_roce_srst(dsaf_dev, false);
|
||||
/* do reset or de-reset according to the flag */
|
||||
if (!dereset) {
|
||||
/* reset rocee-channels in dsaf and rocee */
|
||||
dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK,
|
||||
false);
|
||||
dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, false);
|
||||
} else {
|
||||
/* Configure dsaf tx roce correspond to port map and sl map */
|
||||
/* configure dsaf tx roce correspond to port map and sl map */
|
||||
mp = dsaf_read_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG);
|
||||
for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
|
||||
dsaf_set_field(mp, 7 << i * 3, i * 3,
|
||||
|
@ -2848,12 +2868,13 @@ int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool enable)
|
|||
sl_map[i][DSAF_ROCE_6PORT_MODE]);
|
||||
dsaf_write_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG, sl);
|
||||
|
||||
/* De-reset rocee-channels in dsaf and rocee */
|
||||
hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK, true);
|
||||
/* de-reset rocee-channels in dsaf and rocee */
|
||||
dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK,
|
||||
true);
|
||||
msleep(SRST_TIME_INTERVAL);
|
||||
hns_dsaf_roce_srst(dsaf_dev, true);
|
||||
dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, true);
|
||||
|
||||
/* Eanble dsaf channel rocee credit */
|
||||
/* enable dsaf channel rocee credit */
|
||||
credit = dsaf_read_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG);
|
||||
dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 0);
|
||||
dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
|
||||
|
|
|
@ -305,7 +305,7 @@ struct dsaf_misc_op {
|
|||
void (*cpld_reset_led)(struct hns_mac_cb *mac_cb);
|
||||
int (*cpld_set_led_id)(struct hns_mac_cb *mac_cb,
|
||||
enum hnae_led_state status);
|
||||
/* reset seris function, it will be reset if the dereseet is 0 */
|
||||
/* reset series function, it will be reset if the dereset is 0 */
|
||||
void (*dsaf_reset)(struct dsaf_device *dsaf_dev, bool dereset);
|
||||
void (*xge_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset);
|
||||
void (*xge_core_srst)(struct dsaf_device *dsaf_dev, u32 port,
|
||||
|
@ -313,6 +313,9 @@ struct dsaf_misc_op {
|
|||
void (*ge_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset);
|
||||
void (*ppe_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset);
|
||||
void (*ppe_comm_srst)(struct dsaf_device *dsaf_dev, bool dereset);
|
||||
void (*hns_dsaf_srst_chns)(struct dsaf_device *dsaf_dev, u32 msk,
|
||||
bool dereset);
|
||||
void (*hns_dsaf_roce_srst)(struct dsaf_device *dsaf_dev, bool dereset);
|
||||
|
||||
phy_interface_t (*get_phy_if)(struct hns_mac_cb *mac_cb);
|
||||
int (*get_sfp_prsnt)(struct hns_mac_cb *mac_cb, int *sfp_prsnt);
|
||||
|
@ -445,10 +448,6 @@ int hns_dsaf_get_mac_entry_by_index(
|
|||
|
||||
void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb);
|
||||
|
||||
void hns_dsaf_srst_chns(struct dsaf_device *dsaf_dev, u32 msk, bool enable);
|
||||
|
||||
void hns_dsaf_roce_srst(struct dsaf_device *dsaf_dev, bool enable);
|
||||
|
||||
int hns_dsaf_ae_init(struct dsaf_device *dsaf_dev);
|
||||
void hns_dsaf_ae_uninit(struct dsaf_device *dsaf_dev);
|
||||
|
||||
|
|
|
@ -26,6 +26,8 @@ enum _dsm_rst_type {
|
|||
HNS_XGE_CORE_RESET_FUNC = 0x3,
|
||||
HNS_XGE_RESET_FUNC = 0x4,
|
||||
HNS_GE_RESET_FUNC = 0x5,
|
||||
HNS_DSAF_CHN_RESET_FUNC = 0x6,
|
||||
HNS_ROCE_RESET_FUNC = 0x7,
|
||||
};
|
||||
|
||||
const u8 hns_dsaf_acpi_dsm_uuid[] = {
|
||||
|
@ -241,11 +243,11 @@ static void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
|
|||
* bit18-19 for com/dfx
|
||||
* @enable: false - request reset , true - drop reset
|
||||
*/
|
||||
void hns_dsaf_srst_chns(struct dsaf_device *dsaf_dev, u32 msk, bool enable)
|
||||
void hns_dsaf_srst_chns(struct dsaf_device *dsaf_dev, u32 msk, bool dereset)
|
||||
{
|
||||
u32 reg_addr;
|
||||
|
||||
if (!enable)
|
||||
if (!dereset)
|
||||
reg_addr = DSAF_SUB_SC_DSAF_RESET_REQ_REG;
|
||||
else
|
||||
reg_addr = DSAF_SUB_SC_DSAF_RESET_DREQ_REG;
|
||||
|
@ -253,9 +255,27 @@ void hns_dsaf_srst_chns(struct dsaf_device *dsaf_dev, u32 msk, bool enable)
|
|||
dsaf_write_sub(dsaf_dev, reg_addr, msk);
|
||||
}
|
||||
|
||||
void hns_dsaf_roce_srst(struct dsaf_device *dsaf_dev, bool enable)
|
||||
/**
|
||||
* hns_dsaf_srst_chns - reset dsaf channels
|
||||
* @dsaf_dev: dsaf device struct pointer
|
||||
* @msk: xbar channels mask value:
|
||||
* bit0-5 for xge0-5
|
||||
* bit6-11 for ppe0-5
|
||||
* bit12-17 for roce0-5
|
||||
* bit18-19 for com/dfx
|
||||
* @enable: false - request reset , true - drop reset
|
||||
*/
|
||||
void
|
||||
hns_dsaf_srst_chns_acpi(struct dsaf_device *dsaf_dev, u32 msk, bool dereset)
|
||||
{
|
||||
if (!enable) {
|
||||
hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
|
||||
HNS_DSAF_CHN_RESET_FUNC,
|
||||
msk, dereset);
|
||||
}
|
||||
|
||||
void hns_dsaf_roce_srst(struct dsaf_device *dsaf_dev, bool dereset)
|
||||
{
|
||||
if (!dereset) {
|
||||
dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_ROCEE_RESET_REQ_REG, 1);
|
||||
} else {
|
||||
dsaf_write_sub(dsaf_dev,
|
||||
|
@ -267,6 +287,12 @@ void hns_dsaf_roce_srst(struct dsaf_device *dsaf_dev, bool enable)
|
|||
}
|
||||
}
|
||||
|
||||
void hns_dsaf_roce_srst_acpi(struct dsaf_device *dsaf_dev, bool dereset)
|
||||
{
|
||||
hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
|
||||
HNS_ROCE_RESET_FUNC, 0, dereset);
|
||||
}
|
||||
|
||||
static void
|
||||
hns_dsaf_xge_core_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
|
||||
u32 port, bool dereset)
|
||||
|
@ -575,6 +601,8 @@ struct dsaf_misc_op *hns_misc_op_get(struct dsaf_device *dsaf_dev)
|
|||
misc_op->ge_srst = hns_dsaf_ge_srst_by_port;
|
||||
misc_op->ppe_srst = hns_ppe_srst_by_port;
|
||||
misc_op->ppe_comm_srst = hns_ppe_com_srst;
|
||||
misc_op->hns_dsaf_srst_chns = hns_dsaf_srst_chns;
|
||||
misc_op->hns_dsaf_roce_srst = hns_dsaf_roce_srst;
|
||||
|
||||
misc_op->get_phy_if = hns_mac_get_phy_if;
|
||||
misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt;
|
||||
|
@ -591,6 +619,8 @@ struct dsaf_misc_op *hns_misc_op_get(struct dsaf_device *dsaf_dev)
|
|||
misc_op->ge_srst = hns_dsaf_ge_srst_by_port_acpi;
|
||||
misc_op->ppe_srst = hns_ppe_srst_by_port_acpi;
|
||||
misc_op->ppe_comm_srst = hns_ppe_com_srst;
|
||||
misc_op->hns_dsaf_srst_chns = hns_dsaf_srst_chns_acpi;
|
||||
misc_op->hns_dsaf_roce_srst = hns_dsaf_roce_srst_acpi;
|
||||
|
||||
misc_op->get_phy_if = hns_mac_get_phy_if_acpi;
|
||||
misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt;
|
||||
|
@ -603,3 +633,18 @@ struct dsaf_misc_op *hns_misc_op_get(struct dsaf_device *dsaf_dev)
|
|||
|
||||
return (void *)misc_op;
|
||||
}
|
||||
|
||||
static int hns_dsaf_dev_match(struct device *dev, void *fwnode)
|
||||
{
|
||||
return dev->fwnode == fwnode;
|
||||
}
|
||||
|
||||
struct
|
||||
platform_device *hns_dsaf_find_platform_device(struct fwnode_handle *fwnode)
|
||||
{
|
||||
struct device *dev;
|
||||
|
||||
dev = bus_find_device(&platform_bus_type, NULL,
|
||||
fwnode, hns_dsaf_dev_match);
|
||||
return dev ? to_platform_device(dev) : NULL;
|
||||
}
|
||||
|
|
|
@ -34,5 +34,6 @@
|
|||
#define DSAF_LED_ANCHOR_B 5
|
||||
|
||||
struct dsaf_misc_op *hns_misc_op_get(struct dsaf_device *dsaf_dev);
|
||||
|
||||
struct
|
||||
platform_device *hns_dsaf_find_platform_device(struct fwnode_handle *fwnode);
|
||||
#endif
|
||||
|
|
|
@ -78,10 +78,10 @@
|
|||
#define DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG 0xA88
|
||||
#define DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG 0xA8C
|
||||
#define DSAF_SUB_SC_DSAF_RESET_REQ_REG 0xAA8
|
||||
#define DSAF_SUB_SC_ROCEE_RESET_REQ_REG 0xA50
|
||||
#define DSAF_SUB_SC_DSAF_RESET_DREQ_REG 0xAAC
|
||||
#define DSAF_SUB_SC_ROCEE_CLK_DIS_REG 0x32C
|
||||
#define DSAF_SUB_SC_ROCEE_RESET_REQ_REG 0xA50
|
||||
#define DSAF_SUB_SC_ROCEE_RESET_DREQ_REG 0xA54
|
||||
#define DSAF_SUB_SC_ROCEE_CLK_DIS_REG 0x32C
|
||||
#define DSAF_SUB_SC_ROCEE_CLK_EN_REG 0x328
|
||||
#define DSAF_SUB_SC_LIGHT_MODULE_DETECT_EN_REG 0x2060
|
||||
#define DSAF_SUB_SC_TCAM_MBIST_EN_REG 0x2300
|
||||
|
|
Loading…
Reference in New Issue